From 63a1ec42cc6b0a3e63112535e07c24e68d798397 Mon Sep 17 00:00:00 2001 From: Thi Tran Date: Fri, 11 Jan 2013 10:21:08 -0600 Subject: Allow VSBE to access 0x1007 via faked SCOM reg 0x50007 Change-Id: I7d942bd15e5add2c0fc0adeda6209d9eba45a3aa Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2920 Tested-by: Jenkins Server Reviewed-by: Brian H. Horton Reviewed-by: A. Patrick Williams III --- src/usr/hwpf/hwp/poreve_errors.xml | 136 +++++++++++++++++++++++++++++++ src/usr/hwpf/makefile | 3 +- src/usr/pore/poreve/porevesrc/pib2cfam.C | 73 ++++++++--------- src/usr/pore/poreve/porevesrc/pib2cfam.H | 51 ++++++------ 4 files changed, 200 insertions(+), 63 deletions(-) create mode 100644 src/usr/hwpf/hwp/poreve_errors.xml (limited to 'src/usr') diff --git a/src/usr/hwpf/hwp/poreve_errors.xml b/src/usr/hwpf/hwp/poreve_errors.xml new file mode 100644 index 000000000..303e66194 --- /dev/null +++ b/src/usr/hwpf/hwp/poreve_errors.xml @@ -0,0 +1,136 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RC_POREVE_NO_PIB_MODEL + + Signalled by Pore::pibMaster(). This will never happen; The PoreVe has + not configured a PIB bus. + + + + + RC_POREVE_NO_OCI_MODEL + + Signalled by Pore::ociMaster(). This will never happen; The PoreVe has + not configured an OCI bus. + + + + + RC_POREVE_PORE_OPERATION_ERROR + + Signalled by Pore::operation(). An error occurred during an attempted + register access of the PORE model. + + + + + RC_POREVE_PORE_NOT_MAPPED_ON_BUS + + Signalled by Bus::operation(). No bus slave claimed the transaction, + i.e., an attempted access of an unmapped address. + + + + + RC_POREVE_BUS_SLAVE_PERMISSION_DENIED + + Signalled by Bus::operation(). The access mode was not permitted by the + slave permissions. See the FAPI_ERR() log for details. + + + + + RC_POREVE_HOOKMANAGER_INCONSISTENCY + + Signalled by HookManager::runHooks(). An inconsistency in the HookManager + data structures was detected. See the FAPI_ERR() log for details. + + + + + RC_POREVE_PIB2CFAM_ERROR + + Signalled by Pib2Cfam::operation(). An error occurred during an access of + the virtual Pib2Cfam unit - either a read/write access error or an + attempted access of a non-modeled register. + + + + + RC_POREVE_FASTI2C_ERROR + + Signalled by FastI2cController::operation(). An error occurred during an + access of a FastI2cController. To see the FAPI_ERR() log you may need to + recompile the PoreVe with -DDEBUG_FASTI2C=1. + + + + + RC_POREVE_LPC_ERROR + + Signalled by LpcController::operation(). An error occurred during an + access of a LpcController. To see the FAPI_ERR() log you may need to + recompile the PoreVe with -DDEBUG_FASTI2C=1. + + + + + RC_POREVE_PIBMEM_CONTROL_ERROR + + Signalled by Pibmem::operation(). An error occurred during an access of a + PIBMEM control register. See the FAPI_ERR() log for details. + + + + + RC_POREVE_PIB_MEMORY_ACCESS_ERROR + + Signalled by PibMemory::operation(). An error occurred during an access + of a PibMemory. See the FAPI_ERR() log for details as well as the Model + Error state of the PoreVe. + + + + + RC_POREVE_OCI_MEMORY_ACCESS_ERROR + + Signalled by OciMemory::operation(). An error occurred during an access + of an OciMemory. See the FAPI_ERR() log for details as well as the Model + Error state of the PoreVe. + + + + + RC_POREVE_OCI_SLAVE_ERROR + + Signalled by OciSlave access methods. An error occurred during an access + of an Oci Slave. + + + diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 761536784..0cfab7f89 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -74,7 +74,8 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/runtime_errors/p8_poregpe_errors.xml \ hwp/runtime_errors/p8_pba_init_errors.xml \ hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup_errors.xml \ - hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init_errors.xml + hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init_errors.xml \ + hwp/poreve_errors.xml ## these get generated into obj/genfiles/AttributeIds.H HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \ diff --git a/src/usr/pore/poreve/porevesrc/pib2cfam.C b/src/usr/pore/poreve/porevesrc/pib2cfam.C index 82cabe313..689c456b7 100644 --- a/src/usr/pore/poreve/porevesrc/pib2cfam.C +++ b/src/usr/pore/poreve/porevesrc/pib2cfam.C @@ -1,34 +1,34 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/pore/poreve/porevesrc/pib2cfam.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/pib2cfam.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ // -*- mode: C++; c-file-style: "linux"; -*- -// $Id: pib2cfam.C,v 1.11 2012/04/02 16:27:58 jeshua Exp $ +// $Id: pib2cfam.C,v 1.14 2013/01/11 15:54:22 thi Exp $ /// \file pib2cfam.C /// \brief A simple PibSlave that maps a small range of PIB addresses to CFAM /// addresses. #include "pib2cfam.H" + using namespace vsbe; @@ -54,7 +54,9 @@ translateAddress(uint32_t address, fapi::Target* i_target) frc = FAPI_ATTR_GET( ATTR_FSI_GP_REG_SCOM_ACCESS, i_target, fsi_gpreg_scom_access ); if(!frc.ok()) { - FAPI_ERR( "Unable to get ATTR_FSI_GP_REG_SCOM_ACCESS for target" ); + FAPI_ERR( "Unable to get ATTR_FSI_GP_REG_SCOM_ACCESS for target\n" ); +//JDS TODO - create an actual fapi error +// FAPI_SET_HWP_ERROR( frc, "Unable to get ATTR_FSI_GP_REG_SCOM_ACCESS for target\n" ); } @@ -77,7 +79,7 @@ Pib2Cfam::operation(Transaction& io_transaction) case ACCESS_MODE_READ: switch (io_transaction.iv_address) { - + case 0x00050007: case 0x00050012: case 0x00050013: case 0x00050014: @@ -100,7 +102,6 @@ Pib2Cfam::operation(Transaction& io_transaction) } break; default: - FAPI_SET_HWP_ERROR(rc,RC_POREVE_PIB2CFAM_ME_NOT_MAPPED_IN_MEMORY); me = ME_NOT_MAPPED_IN_MEMORY; } break; @@ -131,22 +132,20 @@ Pib2Cfam::operation(Transaction& io_transaction) case 0x00050019: case 0x0005001A: - FAPI_SET_HWP_ERROR(rc, - RC_POREVE_PIB2CFAM_ME_BUS_SLAVE_PERMISSION_DENIED); - me = ME_BUS_SLAVE_PERMISSION_DENIED; - break; + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB2CFAM_ERROR); + me = ME_BUS_SLAVE_PERMISSION_DENIED; + break; default: - FAPI_SET_HWP_ERROR(rc,RC_POREVE_PIB2CFAM_ME_NOT_MAPPED_IN_MEMORY); - me = ME_NOT_MAPPED_IN_MEMORY; + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB2CFAM_ERROR); + me = ME_NOT_MAPPED_IN_MEMORY; } break; default: - FAPI_SET_HWP_ERROR(rc, - RC_POREVE_PIB2CFAM_ME_BUS_SLAVE_PERMISSION_DENIED); - me = ME_BUS_SLAVE_PERMISSION_DENIED; - break; + FAPI_SET_HWP_ERROR(rc, RC_POREVE_PIB2CFAM_ERROR); + me = ME_BUS_SLAVE_PERMISSION_DENIED; + break; } io_transaction.busError(me); return rc; diff --git a/src/usr/pore/poreve/porevesrc/pib2cfam.H b/src/usr/pore/poreve/porevesrc/pib2cfam.H index 329d3f0a3..2220323c8 100644 --- a/src/usr/pore/poreve/porevesrc/pib2cfam.H +++ b/src/usr/pore/poreve/porevesrc/pib2cfam.H @@ -1,29 +1,29 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/pore/poreve/porevesrc/pib2cfam.H $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/pore/poreve/porevesrc/pib2cfam.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ #ifndef __VSBE_PIB2CFAM_H #define __VSBE_PIB2CFAM_H -// $Id: pib2cfam.H,v 1.3 2011/06/21 00:07:35 bcbrock Exp $ +// $Id: pib2cfam.H,v 1.4 2013/01/11 15:53:49 thi Exp $ /// \file pib2cfam.H /// \brief A temporary hack while waiting for hardware updates - a simple @@ -36,10 +36,10 @@ namespace vsbe { class Pib2Cfam; /// PIB base address of PIB range mapped by Pib2Cfam - const uint32_t PIB2CFAM_PIB_BASE = 0x00050012; + const uint32_t PIB2CFAM_PIB_BASE = 0x00050007; /// Number of PIB addresses mapped by Pib2Cfam - const int PIB2CFAM_PIB_SIZE = ((0x0005001b - 0x00050012) + 1); + const int PIB2CFAM_PIB_SIZE = ((0x0005001b - 0x00050007) + 1); } @@ -69,6 +69,7 @@ public: /// /// The following PIB registers are mapped to CFAM registers: /// + /// - PIB 0x00050007 -> CFAM 0x1007, FSI2PIB.STATUS, R /// - PIB 0x00050012 -> CFAM 0x1012, FSIGP3, R/W /// - PIB 0x00050013 -> CFAM 0x1013, FSIGP4, R/W /// - PIB 0x00050014 -> CFAM 0x1014, FSIGP5, R/W -- cgit v1.2.1