From 3653c5d44e88968b1f09f73eda056c3898174a22 Mon Sep 17 00:00:00 2001 From: Christian Geddes Date: Mon, 11 Mar 2019 18:01:45 -0500 Subject: Skip establish ex chiplet step (15.3) during Axone for now For some reason when we set the multi-cast groups it breaks some multi-cast registers in simics that PRD uses after isteps. For now just skip this step so we can continue with the IPL. Change-Id: I2511ecb35ab32dae1d9a334964bc88317de74ef0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73149 Tested-by: Jenkins Server Reviewed-by: Matt Derksen Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Corey V. Swenson Reviewed-by: Daniel M. Crowell --- src/usr/isteps/istep15/host_establish_ex_chiplet.C | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/usr/isteps') diff --git a/src/usr/isteps/istep15/host_establish_ex_chiplet.C b/src/usr/isteps/istep15/host_establish_ex_chiplet.C index e96394007..be5640167 100644 --- a/src/usr/isteps/istep15/host_establish_ex_chiplet.C +++ b/src/usr/isteps/istep15/host_establish_ex_chiplet.C @@ -53,6 +53,7 @@ void* host_establish_ex_chiplet (void *io_pArgs) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_establish_ex_chiplet entry" ); ISTEP_ERROR::IStepError l_StepError; + #ifndef CONFIG_AXONE_BRING_UP errlHndl_t l_errl = NULL; do { //Use targeting code to get a list of all processors @@ -77,6 +78,7 @@ void* host_establish_ex_chiplet (void *io_pArgs) } } }while(0); + #endif // end task, returning any errorlogs to IStepDisp TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_establish_ex_chiplet exit" ); -- cgit v1.2.1