From 8fac481d825883154ca20612ca0a69bc52f02618 Mon Sep 17 00:00:00 2001 From: Doug Gilbert Date: Tue, 23 Apr 2013 14:10:52 -0500 Subject: Inter-processor communications for multinode RTC: 63128 Change-Id: Ica27c7f714bc8b874c9bccb663a32d3cfba37c5a Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4193 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III --- src/usr/intr/test/intrtest.H | 50 -------------------------------------------- 1 file changed, 50 deletions(-) (limited to 'src/usr/intr/test') diff --git a/src/usr/intr/test/intrtest.H b/src/usr/intr/test/intrtest.H index 56670329e..c653d6609 100644 --- a/src/usr/intr/test/intrtest.H +++ b/src/usr/intr/test/intrtest.H @@ -133,56 +133,6 @@ class IntrTest: public CxxTest::TestSuite } } - /** - * @brief Register an interrupt message queue, force an interrupt, - * then handle the interrupt. - */ - void test_intr( void ) - { - - // DISABLE in VBU - if( TARGETING::is_vpo() ) - { - return; - } - - errlHndl_t err = NULL; - - // Need to register a msgq - msg_q_t msgQ = msg_q_create(); - err = INTR::registerMsgQ(msgQ,0,INTR::ISN_INTERPROC); - if(err) - { - TS_FAIL("Errl from INTR::registerMsgQ()"); - delete err; - err = NULL; - } - - // Force an interrupt by writing to the MFFR on master - volatile uint8_t * mfrr = - reinterpret_cast(iv_masterAddr+12); - *(mfrr) = 0x55; - - TRACFCOMP(g_trac_intr,"Waiting for IPI interrupt"); - msg_t* msg = msg_wait(msgQ); // wait for interrupt msg - TRACFCOMP(g_trac_intr,"Interrupt handled! Type=%lx",msg->data[0]); - if(msg->data[0] != INTR::INTERPROC_XISR) - { - TS_FAIL("INTR::unexpected interrupt type %lx",msg->data[0]); - } - msg_respond(msgQ,msg); - - msgQ = INTR::unRegisterMsgQ(INTR::ISN_INTERPROC); - if(msgQ) - { - msg_q_destroy(msgQ); - } - else - { - TS_FAIL("INTR::unRegisterMsgQ failed"); - } - } - // This checks the enablePsiIntr. Even though the master proc // is already configured it does not use this interface // and there are no other processor currently configured in simics -- cgit v1.2.1