From 461eb82edd2ea88af71bcb543903944c1b12a21a Mon Sep 17 00:00:00 2001 From: Adam Muhle Date: Mon, 10 Jun 2013 09:09:42 -0500 Subject: OCC Reset Procedures for Stradale RTC: 73049 Change-Id: If08829a73aa18e04788c85ced6eb452c6f0a1e1d Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4919 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert Reviewed-by: Daniel M. Crowell Reviewed-by: A. Patrick Williams III --- src/usr/hwpf/hwp/occ/makefile | 6 + .../hwp/occ/occ_procedures/p8_pm_prep_for_reset.C | 886 +++++++++++++++++++++ .../hwp/occ/occ_procedures/p8_pm_prep_for_reset.H | 126 +++ .../occ/occ_procedures/proc_cpu_special_wakeup.C | 131 +++ .../occ/occ_procedures/proc_cpu_special_wakeup.H | 105 +++ src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.C | 455 +++++++++++ src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.H | 76 ++ .../runtime_errors/p8_pm_prep_for_reset_errors.xml | 9 +- 8 files changed, 1793 insertions(+), 1 deletion(-) create mode 100644 src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C create mode 100644 src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.H create mode 100644 src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.C create mode 100644 src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.H create mode 100644 src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.C create mode 100755 src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.H (limited to 'src/usr/hwpf/hwp') diff --git a/src/usr/hwpf/hwp/occ/makefile b/src/usr/hwpf/hwp/occ/makefile index 575741ec9..3a7473721 100644 --- a/src/usr/hwpf/hwp/occ/makefile +++ b/src/usr/hwpf/hwp/occ/makefile @@ -66,6 +66,12 @@ OBJS = occ.o \ p8_pm_pmc_firinit.o \ p8_cpu_special_wakeup.o +#These procedures are included per Stradale's request so +#they can implement OCC Reset. +OBJS+= p8_pm_prep_for_reset.o \ + proc_cpu_special_wakeup.o \ + p8_pmc_force_vsafe.o + ## NOTE: add a new directory onto the vpaths when you add a new HWP ## EXAMPLE: # VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/occ/ diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C new file mode 100644 index 000000000..08cc3db9d --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C @@ -0,0 +1,886 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: p8_pm_prep_for_reset.C,v 1.18 2013/04/12 01:28:32 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_prep_for_reset.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com +// *! +/// \file p8_pm_prep_for_reset.C +/// \brief Initialize powermanagement +/// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ +/// +/// +/// +/// \version -------------------------------------------------------------------------- +/// \version 1.5 rmaier 09/19/12 Added review feedback +/// \version -------------------------------------------------------------------------- +/// \version 1.4 rmaier 09/17/12 Fixed error when calling p8_ocb_init.C. +/// \version -------------------------------------------------------------------------- +/// \version 1.1 rmaier 08/23/12 Renaming proc_ to p8_ +/// \version -------------------------------------------------------------------------- +/// \version 1.3 rmaier 2012/07/17 Added review feedback +/// \version -------------------------------------------------------------------------- +/// \version 1.2 rmaier 2012/03/13 Added return code handling +/// \version -------------------------------------------------------------------------- +/// \version 1.1 rmaier 2012/02/28 Added calls to subroutines +/// \version -------------------------------------------------------------------------- +/// \version 1.0 rmaier 2012/02/01 Initial Version +/// \version --------------------------------------------------------------------------- +/// +/// High-level procedure flow: +/// +/// \verbatim +/// +/// +/// - call p8_occ_control.C *chiptarget, ENUM:OCC_STOP ppc405_reset_ctrl = 2 +/// - OCC PPC405 put into reset +/// - PMC moves to Vsafe value due to heartbeat loss +/// +/// - evaluate RC +/// +/// - call p8_cpu_special_wakeup.C *chiptarget, ENUM:OCC_SPECIAL_WAKEUP +/// - For each chiplet, put into Special Wake-up via the OCC special wake-up bit +/// +/// - evaluate RC +/// +/// - call p8_pmc_force_vsafe.C *chiptarget, +/// - Forces the Vsafe value into the voltage controller +/// +/// - evaluate RC +/// +/// - call p8_pcbs_init.C *chiptarget, ENUM:PCBSPM_RESET +/// +/// - evaluate RC +/// +/// - call p8_pmc_init.C *chiptarget, ENUM:PMC_RESET +/// - Issue reset to the PMC +/// +/// - evaluate RC +/// +/// - call p8_poresw_init.C *chiptarget, ENUM:PORESLW_RESET +/// +/// - evaluate RC +/// +/// - call p8_poregpe_init.C *chiptarget, ENUM:POREGPE_RESET +/// +/// - evaluate RC +/// +/// - call p8_oha_init.C *chiptarget, ENUM:OHA_RESET +/// +/// - evaluate RC +/// +/// - call p8_pba_init.C *chiptarget, ENUM:PBA_RESET +/// +/// - evaluate RC +/// +/// - call p8_occ_sram_init.C *chiptarget, ENUM:OCC_SRAM_RESET +/// +/// - evaluate RC +/// +/// - call p8_ocb_init .C *chiptarget, ENUM:OCC_OCB_RESET +/// - evaluate RC +/// +/// +/// \endverbatim +/// + + +//------------------------------------------------------------------------------ +//---------------------------------------------------------------------- +// eCMD Includes +//---------------------------------------------------------------------- +#include + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include +#include "p8_scom_addresses.H" +#include "p8_pm_prep_for_reset.H" +#include "p8_cpu_special_wakeup.H" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- +// Address definition for chiplet EX01 with base address 0x10000000 +// Example: getscom pu.ex 10000001 -c3 ---> scom address 0x13000001 + +CONST_UINT64_T( EX_PMGP0_0x150F0100 , ULL(0x150F0100) ); + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- +// \temporary +fapi::ReturnCode corestat(const fapi::Target& i_target); + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + +/// i_primary_chip_target Primary Chip target which will be passed +/// to all the procedures +/// i_secondary_chip_target Secondary Chip target will be passed for +/// pmc_init -reset only if it is DCM otherwise +/// this should be NULL. + +fapi::ReturnCode +p8_pm_prep_for_reset( const fapi::Target &i_primary_chip_target , + const fapi::Target &i_secondary_chip_target ) +{ + +// Procedures executed in this file +/// FAPI_EXEC_HWP(rc, p8_occ_control, i_primary_chip_target, PM_RESET, 0); +/// FAPI_EXEC_HWP(rc, proc_cpu_special_wakeup, l_exChiplets[j], SPCWKUP_ENABLE , HOST); +/// FAPI_EXEC_HWP(rc, p8_pmc_force_vsafe, i_primary_chip_target); +/// FAPI_EXEC_HWP(rc, p8_pcbs_init, i_primary_chip_target, PM_RESET); +/// FAPI_EXEC_HWP(rc, p8_pmc_init, i_primary_chip_target, i_secondary_chip_target, PM_RESET); +/// FAPI_EXEC_HWP(rc, p8_poreslw_init, i_primary_chip_target, PM_RESET); +/// FAPI_EXEC_HWP(rc, p8_poregpe_init, i_primary_chip_target, PM_RESET, GPEALL ); +/// FAPI_EXEC_HWP(rc, p8_oha_init, i_primary_chip_target, PM_RESET ); +/// FAPI_EXEC_HWP(rc, p8_pba_init, i_primary_chip_target, PM_RESET ); +/// FAPI_EXEC_HWP(rc, p8_occ_sram_init, i_primary_chip_target, PM_RESET ); +/// FAPI_EXEC_HWP(rc, p8_ocb_init, i_primary_chip_target, PM_RESET,0 , 0, 0, 0, 0, 0 ); + + + + fapi::ReturnCode rc; + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + + std::vector l_exChiplets; + ecmdDataBufferBase data(64); + ecmdDataBufferBase mask(64); + + // std::vector l_chiplets; + fapi::Target dummy; + + do + { + + FAPI_INF("Executing p8_pm_prep_for_reset ...."); + + if ( i_secondary_chip_target.getType() == TARGET_TYPE_NONE ) + { + if ( i_primary_chip_target.getType() == TARGET_TYPE_NONE ) + { + FAPI_ERR("Set primay target properly for SCM " ) ; + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PREP_TARGET_ERR); + break; + } + FAPI_DBG("Running on SCM"); + } + else + { + FAPI_DBG("Running on DCM"); + } + + // ****************************************************************** + // Mask the FIRs + // ****************************************************************** + + FAPI_INF("Executing:p8_pm_firinit in mode PM_RESET"); + + FAPI_EXEC_HWP(rc, p8_pm_firinit, i_primary_chip_target , PM_RESET ); + if (rc) + { + FAPI_ERR("ERROR: p8_pm_firinit detected failed result"); + break; + } + + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + + FAPI_EXEC_HWP(rc, p8_pm_firinit, i_secondary_chip_target , PM_RESET ); + if (rc) + { + FAPI_ERR("ERROR: p8_pm_firinit detected failed result"); + break; + } + } + + + // ****************************************************************** + // Put OCC PPC405 into reset + // ****************************************************************** + // ****************************************************************** + // - call p8_occ_control.C *chiptarget, ENUM:OCC_STOP ppc405_reset_ctrl = 2s + // + // ****************************************************************** + + FAPI_INF("Put OCC PPC405 into reset"); + FAPI_DBG("Executing: p8_occ_control.C"); + + FAPI_EXEC_HWP(rc, p8_occ_control, i_primary_chip_target, PPC405_RESET_ON, 0); + if (rc) + { + FAPI_ERR("p8_occ_control: Failed to prepare OCC for RESET. With rc = 0x%x", (uint32_t)rc); + break; + } + + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(rc, p8_occ_control, i_secondary_chip_target, PPC405_RESET_ON, 0); + if (rc) + { + FAPI_ERR("p8_occ_control: Failed to prepare OCC for RESET. With rc = 0x%x", (uint32_t)rc); + break; + } + + // rc = fapiGetScom( i_secondary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 secondary = %016llX", data.getDoubleWord(0) ); + } + + // ****************************************************************** + // Put all EX chiplet special wakeup + // ****************************************************************** + // - call proc_cpu_special_wakeup.C *chiptarget, ENUM:OCC_SPECIAL_WAKEUP + // - For each chiplet, put into Special Wake-up via the OCC special wake-up bit + + //////////////////////// PRIMARY TARGET //////////////////////////////// + rc = fapiGetChildChiplets ( i_primary_chip_target, + TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + TARGET_STATE_PRESENT); + if (rc) + { + FAPI_ERR("Error from fapiGetChildChiplets!"); + break; + } + + FAPI_DBG("Number of EX chiplet on primary => %u ", l_exChiplets.size()); + + // Iterate through the returned chiplets + for (uint8_t j=0; j < l_exChiplets.size(); j++) + { + + // Determine if it's functional + rc = FAPI_ATTR_GET( ATTR_FUNCTIONAL, + &l_exChiplets[j], + l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL error"); + break; + } + + if ( l_functional ) + { + // The ex is functional let's build the SCOM address + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[j], l_ex_number); + FAPI_DBG("Running special wakeup on ex chiplet %d ", l_ex_number); + + // Set special wakeup for EX + // Commented due to attribute errors + //FAPI_EXEC_HWP(rc, proc_cpu_special_wakeup, l_exChiplets[j], SPCWKUP_ENABLE , HOST); + rc = fapiSpecialWakeup(l_exChiplets[j], true); + if (rc) + { + FAPI_ERR("fapiSpecialWakeup: Failed to put CORE %d into special wakeup. With rc = 0x%x", l_ex_number, (uint32_t)rc); + break; + } + + } + } // chiplet loop + + // Exit if error + if (!rc.ok()) + { + break; + } + + + // rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // + // FAPI_DBG(" EX_PMGP0_0x150F0100_prim = %016llX", data.getDoubleWord(0) ); + + //////////////////////// SECONDARY TARGET //////////////////////////////// + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + rc = fapiGetChildChiplets ( i_secondary_chip_target, + TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + TARGET_STATE_PRESENT); + if (rc) + { + FAPI_ERR("Error from fapiGetChildChiplets!"); + break; + } + + FAPI_DBG("Number of EX chiplet on secondary => %u ", l_exChiplets.size()); + + // Iterate through the returned chiplets + for (uint8_t j=0; j < l_exChiplets.size(); j++) + { + + // Determine if it's functional + rc = FAPI_ATTR_GET( ATTR_FUNCTIONAL, + &l_exChiplets[j], + l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL error"); + break; + } + + if ( l_functional ) + { + // The ex is functional + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[j], l_ex_number); + FAPI_DBG("Running special wakeup on EX chiplet %d ", l_ex_number); + + // Set special wakeup for EX + // Commented due to attribute errors + //FAPI_EXEC_HWP(rc, proc_cpu_special_wakeup, l_exChiplets[j], SPCWKUP_ENABLE , HOST); + rc = fapiSpecialWakeup(l_exChiplets[j], true); + if (rc) + { + FAPI_ERR("fapiSpecialWakeup: Failed to put CORE %d into special wakeup. With rc = 0x%x", l_ex_number, (uint32_t)rc); + break; + } + } + } // chiplet loop + + // Exit if error + if (!rc.ok()) + { + break; + } + + + // rc = fapiGetScom( i_secondary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + } + + // ****************************************************************** + // Force Vsafe value into voltage controller + // ****************************************************************** + // - call p8_pmc_force_vsafe.C *chiptarget, + // - Forces the Vsafe value into the voltage controller + // + + FAPI_INF("Force Vsafe value into voltage controller"); + FAPI_DBG("Executing: p8_pmc_force_vsafe.C"); + + //////////////////////// PRIMARY TARGET //////////////////////////////// + + FAPI_EXEC_HWP(rc, p8_pmc_force_vsafe, i_primary_chip_target); + if (rc) + { + FAPI_ERR("Failed to force Vsafe value into voltage controller. With rc = 0x%x", (uint32_t)rc); + FAPI_ERR("Contining with reset of Power Management functions"); + + //break; + } + +// rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); +// if (rc) +// { +// FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); +// break; +// } +// FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + + //////////////////////// SECONDARY TARGET //////////////////////////////// + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(rc, p8_pmc_force_vsafe, i_secondary_chip_target); + if (rc) + { + FAPI_ERR("Failed to force Vsafe value into voltage controller. With rc = 0x%x", (uint32_t)rc); + FAPI_ERR("Contining with reset of Power Management functions"); + + //break; + } + + // rc = fapiGetScom( i_secondary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + } + + // ****************************************************************** + // Prepare PCBSLV_PM for RESET + // ****************************************************************** + // - call p8_pcbs_init.C *chiptarget, ENUM:PCBSPM_RESET + // + // - p8_pcbs_init internally loops over all enabled chiplets + + FAPI_INF("Prepare PCBSLV_PM for RESET"); + FAPI_DBG("Executing: p8_pcbs_init.C"); + + //////////////////////// PRIMARY TARGET //////////////////////////////// + FAPI_EXEC_HWP(rc, p8_pcbs_init, i_primary_chip_target, PM_RESET); + if (rc) + { + FAPI_ERR("p8_pcbs_init: Failed to prepare PCBSLV_PM for RESET. With rc = 0x%x", (uint32_t)rc); + break; + } + + // >>>>> temp debug only <<<<<< + // rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + + //////////////////////// SECONDARY TARGET //////////////////////////////// + + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + + FAPI_EXEC_HWP(rc, p8_pcbs_init, i_secondary_chip_target, PM_RESET); + if (rc) + { + FAPI_ERR("p8_pcbs_init: Failed to prepare PCBSLV_PM for RESET. With rc = 0x%x", (uint32_t)rc); + break; + } + + // >>>>> temp debug only <<<<<< + // rc = fapiGetScom( i_secondary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + } + + // ****************************************************************** + // Reset PMC + // ****************************************************************** + // - call p8_pmc_init.C *chiptarget, ENUM:PMC_RESET + // + + FAPI_INF("Issue reset to PMC"); + FAPI_DBG("Executing: p8_pmc_init.C"); + + FAPI_EXEC_HWP(rc, p8_pmc_init, i_primary_chip_target, i_secondary_chip_target, PM_RESET); + if (rc) + { + FAPI_ERR("p8_pmc_init: Failed to issue PMC reset. With rc = 0x%x", (uint32_t)rc); + break; + } + + // rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + // ****************************************************************** + // Issue reset to PSS macro + // ****************************************************************** + // - call p8_poreslw_init.C *chiptarget, ENUM:PORESLW_RESET + // + + FAPI_INF("Issue reset to PSS macro"); + FAPI_DBG("Executing: p8_pss_init.C"); + + //////////////////////// PRIMARY TARGET //////////////////////////////// + FAPI_EXEC_HWP(rc, p8_pss_init, i_primary_chip_target, PM_RESET); + if (rc) + { + FAPI_ERR("p8_pss_init: Failed to issue reset to PSS macro. With rc = 0x%x", (uint32_t)rc); + break; + } + + // rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + + //////////////////////// SECONDARY TARGET //////////////////////////////// + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + + FAPI_DBG("FAPI_EXEC_HWP(rc, p8_pss_init, i_secondary_chip_target, PM_RESET);"); + + FAPI_EXEC_HWP(rc, p8_pss_init, i_secondary_chip_target, PM_RESET); + if (rc) + { + FAPI_ERR("p8_pss_init: Failed to issue reset to PSS macro. With rc = 0x%x", (uint32_t)rc); + break; + } + + // rc = fapiGetScom( i_secondary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + } + + // ****************************************************************** + // Issue reset to PORE Sleep/Winkle engine + // ****************************************************************** + // - call p8_poreslw_init.C *chiptarget, ENUM:PORESLW_RESET + + FAPI_INF("Issue reset to PORE Sleep/Winkle engine"); + FAPI_DBG("Executing: p8_poreslw_init.C"); + + //////////////////////// PRIMARY TARGET //////////////////////////////// + FAPI_EXEC_HWP(rc, p8_poreslw_init, i_primary_chip_target, PM_RESET); + if (rc) + { + FAPI_ERR("p8_poreslw_init: Failed to issue reset to PORE Sleep/Winkle engine. With rc = 0x%x", (uint32_t)rc); + break; + } + + // >>>>> temp debug only <<<<<< + // rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + //////////////////////// SECONDARY TARGET //////////////////////////////// + + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(rc, p8_poreslw_init, i_secondary_chip_target, PM_RESET); + if (rc) + { + FAPI_ERR("p8_poreslw_init: Failed to issue reset to PORE Sleep/Winkle engine. With rc = 0x%x", (uint32_t)rc); + break; + } + + // >>>>> temp debug only <<<<<< + // rc = fapiGetScom( i_secondary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + } + + // ****************************************************************** + // Issue reset to PORE General Purpose Engine + // ****************************************************************** + // - call p8_poregpe_init.C *chiptarget, ENUM:POREGPE_RESET + + FAPI_INF("Issue reset to PORE General Purpose Engine"); + FAPI_DBG("Executing: p8_poregpe_init.C"); + + //////////////////////// PRIMARY TARGET //////////////////////////////// + FAPI_EXEC_HWP(rc, p8_poregpe_init, i_primary_chip_target, PM_RESET, GPEALL ); + if (rc) + { + FAPI_ERR("p8_poregpe_init: Failed to issue reset to PORE General Purpose Engine. With rc = 0x%x", (uint32_t)rc); + break; + } + + // rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + //////////////////////// SECONDARY TARGET //////////////////////////////// + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(rc, p8_poregpe_init, i_secondary_chip_target, PM_RESET, GPEALL ); + if (rc) + { + FAPI_ERR("p8_poregpe_init: Failed to issue reset to PORE General Purpose Engine. With rc = 0x%x", (uint32_t)rc); + break; + } + + // rc = fapiGetScom( i_secondary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + } + + // ****************************************************************** + // Issue reset to OHA + // ****************************************************************** + // // - call p8_oha_init.C *chiptarget, ENUM:OHA_RESET + // // + // FAPI_DBG(""); + // // FAPI_DBG("*************************************"); + // FAPI_INF("Issue reset to PORE General Purpose Engine"); + // FAPI_DBG("Executing: p8_oha_init.C"); + // // FAPI_DBG("*************************************"); + // FAPI_DBG("FAPI_EXEC_HWP(rc, p8_oha_init, i_primary_chip_target, PM_RESET );"); + // FAPI_DBG(""); + + // // + // FAPI_EXEC_HWP(rc, p8_oha_init, i_primary_chip_target, PM_RESET ); + // if (rc) + // { + // FAPI_ERR("p8_oha_init: Failed to issue reset to OHA. With rc = 0x%x", (uint32_t)rc); + // break; + // } + + + // rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + // ****************************************************************** + // Issue reset to PBA + // ****************************************************************** + // - call p8_pba_init.C *chiptarget, ENUM:PBA_RESET + // + + FAPI_INF("Issue reset to PBA"); + FAPI_DBG("Executing: p8_pba_init.C"); + + //////////////////////// PRIMARY TARGET //////////////////////////////// + FAPI_EXEC_HWP(rc, p8_pba_init, i_primary_chip_target, PM_RESET ); + if (rc) + { + FAPI_ERR("p8_pba_init: Failed to issue reset to PBA. With rc = 0x%x", (uint32_t)rc); + break; + } + + // rc = fapiGetScom( i_primary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + //////////////////////// SECONDARY TARGET //////////////////////////////// + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(rc, p8_pba_init, i_secondary_chip_target, PM_RESET ); + if (rc) + { + FAPI_ERR("p8_pba_init: Failed to issue reset to PBA. With rc = 0x%x", (uint32_t)rc); + break; + } + + // rc = fapiGetScom( i_secondary_chip_target, EX_PMGP0_0x150F0100 , data); + // if (rc) + // { + // FAPI_ERR("fapiGetScom EX_PMGP0_0x150F0100 failed. With rc = 0x%x", (uint32_t)rc); + // break; + // } + // FAPI_DBG(" EX_PMGP0_0x150F0100 = %016llX", data.getDoubleWord(0) ); + + } + + // ****************************************************************** + // Issue reset to OCC-SRAM + // ****************************************************************** + // - call p8_occ_sram_init.C *chiptarget, ENUM:OCC_SRAM_RESET + // + + FAPI_INF("Issue reset to OCC-SRAM"); + FAPI_DBG("Executing: p8_occ_sram_init.C"); + + //////////////////////// PRIMARY TARGET //////////////////////////////// + FAPI_EXEC_HWP(rc, p8_occ_sram_init, i_primary_chip_target, PM_RESET ); + if (rc) + { + FAPI_ERR("p8_occ_sram_init: Failed to issue reset to OCC-SRAM. With rc = 0x%x", (uint32_t)rc); + break; + } + + //////////////////////// SECONDARY TARGET //////////////////////////////// + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(rc, p8_occ_sram_init, i_secondary_chip_target, PM_RESET ); + if (rc) + { + FAPI_ERR("p8_occ_sram_init: Failed to issue reset to OCC-SRAM. With rc = 0x%x", (uint32_t)rc); + break; + } + } + + // ****************************************************************** + // Issue reset to OCB + // ****************************************************************** + // - call p8_ocb_init.C *chiptarget, ENUM:OCC_OCB_RESET + + FAPI_INF("Issue reset to OCB"); + FAPI_DBG("Executing: p8_ocb_init.C"); + + //////////////////////// PRIMARY TARGET //////////////////////////////// + FAPI_EXEC_HWP(rc, p8_ocb_init, i_primary_chip_target, PM_RESET,0 , 0, 0, 0, 0, 0 ); + if (rc) + { + FAPI_ERR("p8_ocb_init: Failed to issue reset to OCB. With rc = 0x%x", (uint32_t)rc); + break; + } + + //////////////////////// SECONDARY TARGET //////////////////////////////// + if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE ) + { + FAPI_EXEC_HWP(rc, p8_ocb_init, i_secondary_chip_target, PM_RESET,0 , 0, 0, 0, 0, 0 ); + if (rc) + { + FAPI_ERR("p8_ocb_init: Failed to issue reset to OCB. With rc = 0x%x", (uint32_t)rc); + break; + } + } + + } while(0); + fapiDelay(300 , 3000 ); + + FAPI_INF("Exiting p8_pm_prep_for_reset"); + + return rc; +} // Procedure + + +//------------------------------------------------------------------------------ +// Core Status +//------------------------------------------------------------------------------ +fapi::ReturnCode +corestat(const fapi::Target& i_target) +{ + fapi::ReturnCode rc; + + ecmdDataBufferBase data(64); + + std::vector l_exChiplets; + uint8_t l_functional = 0; + uint8_t l_ex_number = 0; + + + FAPI_INF("Core Status ..."); + + rc = fapiGetChildChiplets ( i_target, + TARGET_TYPE_EX_CHIPLET, + l_exChiplets, + TARGET_STATE_FUNCTIONAL); + if (rc) + { + FAPI_ERR("Error from fapiGetChildChiplets!"); + return rc; + } + FAPI_DBG("Number of chiplets => %u", l_exChiplets.size()); + + // Iterate through the returned chiplets + //for (itr = l_exChiplets.begin(); itr != l_exChiplets.end(); itr++) + for (uint8_t c=0; c < l_exChiplets.size(); c++) + { + // Determine if it's functional + //rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, itr, l_functional); + rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[c], l_functional); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL error"); + break; + } + + // With TARGET_STATE_FUNCTIONAL above, this check may be redundant + if ( l_functional ) + { + // Get the core number + //rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, itr, c); + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[c], l_ex_number); + if (rc) + { + FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS error"); + break; + } + + FAPI_DBG("Processing core : %d ", l_ex_number); + + // Read register content + + rc = fapiGetScom( l_exChiplets[c], EX_PERV_SCRATCH0_10013283 , data ); + if (rc) + { + FAPI_ERR("fapiGetScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); + return rc; + } + + FAPI_DBG ("EX_PERV_SCRATCH0_10013283 : %016llX", data.getDoubleWord(0)); + + } + } + + return rc; + +} //corestat + + + +} //end extern C + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.H b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.H new file mode 100644 index 000000000..3dc49870d --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.H @@ -0,0 +1,126 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: p8_pm_prep_for_reset.H,v 1.8 2013/03/27 08:34:05 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_prep_for_reset.H,v $ + +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com +// *! +// *! General Description: +// *! +// *! Prepare powermanagement components for reset +// *! +//------------------------------------------------------------------------------ +// +// constant definitions for . +#define UNIT_CONFIG 0x1 +#define UNIT_RESET 0x2 + +#include "proc_cpu_special_wakeup.H" +#include "p8_pm.H" +#include "p8_poregpe_init.H" +#include "p8_pcbs_init.H" +#include "p8_pmc_init.H" +#include "p8_poreslw_init.H" +#include "p8_poregpe_init.H" +#include "p8_oha_init.H" +#include "p8_pba_init.H" //FIXME was not compiling check with Klaus +#include "p8_occ_sram_init.H" +#include "p8_ocb_init.H" +#include "p8_pss_init.H" +#include "p8_pmc_force_vsafe.H" +#include "p8_occ_control.H" +#include "p8_pm_firinit.H" + + +/** +* @brief Function pointer typedef. +*/ +// typedef fapi::ReturnCode (*p8_occ_control_FP_t) (Target i_target, uint32_t ppc405_reset_ctrl, uint32_t sram_bv_ctrl); +// //typedef fapi::ReturnCode (*p8_cpu_special_wakeup_FP_t)(Target i_target, uint32_t mode); +// //typedef fapi::ReturnCode (*p8_cpu_special_wakeup_FP_t)(Target i_target, uint8_t, uint8_t); + +// typedef fapi::ReturnCode (*p8_pmc_force_vsafe_FP_t) (Target i_target); +// typedef fapi::ReturnCode (*p8_pcbs_init_FP_t) (const fapi::Target&, uint32_t ); +// typedef fapi::ReturnCode (*p8_pmc_init_FP_t) (const fapi::Target&, uint32_t ); +// typedef fapi::ReturnCode (*p8_poreslw_init_FP_t) (const fapi::Target&, uint32_t); +// typedef fapi::ReturnCode (*p8_poregpe_init_FP_t) (const fapi::Target&, uint32_t, uint32_t); +// typedef fapi::ReturnCode (*p8_oha_init_FP_t) (const fapi::Target&, uint32_t); +// typedef fapi::ReturnCode (*p8_pba_init_FP_t) (const fapi::Target&, uint32_t); +// typedef fapi::ReturnCode (*p8_occ_sram_init_FP_t) (const fapi::Target&, uint32_t); +// typedef fapi::ReturnCode (*p8_ocb_init_FP_t) (const fapi::Target&, uint32_t); + typedef fapi::ReturnCode (*p8_pm_prep_for_reset_FP_t) (const fapi::Target &i_primary_chip_target , const fapi::Target &i_secondary_chip_target ); + + +extern "C" +{ + + /// \brief Prepare powermanagement components for reset + /// i_primary_chip_target Primary Chip target which will be passed to all the procedures + /// i_secondary_chip_target Secondary Chip target will be passed for pmc_init -reset only if it is DCM otherwise + + fapi::ReturnCode p8_pm_prep_for_reset(const fapi::Target &i_primary_chip_target , const fapi::Target &i_secondary_chip_target ); + + +// p8_occ_control +// fapi::ReturnCode p8_occ_control(Target &i_target, uint32_t ppc405_reset_ctrl, uint32_t sram_bv_ctrl); + +// // p8_cpu_special_wakeup +// //fapi::ReturnCode p8_cpu_special_wakeup(const Target &i_target, uint32_t mode); +// //fapi::ReturnCode p8_cpu_special_wakeup(const Target &i_target, uint8_t entity, uint8_t operation); + +// // p8_pmc_force_vsafe +// fapi::ReturnCode p8_pmc_force_vsafe(const Target &i_target); + +// // p8_pcbs_init +// fapi::ReturnCode p8_pcbs_init(const Target &i_target, uint32_t mode); + +// // p8_pmc_init +// fapi::ReturnCode p8_pmc_init(const Target &i_target, uint32_t mode); + +// //p8_poreslw_init +// fapi::ReturnCode p8_poreslw_init(const fapi::Target& i_target, uint32_t mode); + +// //p8_poregpe_init +// fapi::ReturnCode p8_poregpe_init(const fapi::Target& i_target, uint32_t mode, uint32_t engine); + +// //p8_oha_init +// fapi::ReturnCode p8_oha_init(const fapi::Target& i_target, uint32_t mode); + +// //p8_pba_init +// fapi::ReturnCode p8_pba_init(const fapi::Target& i_target, uint32_t mode); + +// //p8_occ_sram_init +// fapi::ReturnCode p8_occ_sram_init(const fapi::Target& i_target, uint32_t mode); + +// //p8_ocb_init +// fapi::ReturnCode p8_ocb_init(const fapi::Target& i_target, uint32_t mode); + + +} + + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.C b/src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.C new file mode 100644 index 000000000..2c8bd6392 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.C @@ -0,0 +1,131 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_cpu_special_wakeup.C,v 1.25 2012/10/09 11:04:29 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cpu_special_wakeup.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com +// *! +/// \file p8_pm_init.C +/// \brief Calls each PM unit firinit procedrues to configure the FIRs to +/// predefined types : +/// +/// +/// +/// +/// +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ +/// +/// \todo Review +/// +/// +/// High-level procedure flow: +/// +/// \verbatim +/// - call p8_pm_pmc_firinit.C *chiptarget +/// - evaluate RC +/// +/// - call p8_pm_pba_firinit.C *chiptarget +/// - evaluate RC +/// +/// +/// \endverbatim +/// +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- + + +#include +#include + + + +// #ifdef FAPIECMD +extern "C" { + // #endif + + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- +/// \ input ex_target +// ---------------------------------------------------------------------- +// p8_pm_init +// ---------------------------------------------------------------------- + +fapi::ReturnCode +proc_cpu_special_wakeup(const fapi::Target &i_ex_target, PROC_SPCWKUP_OPS i_operation , PROC_SPCWKUP_ENTITY i_entity ) +{ + + fapi::ReturnCode l_fapi_rc; + + + + // ****************************************************************** + // PMC_FIRS + // ****************************************************************** + + FAPI_DBG(""); + FAPI_EXEC_HWP(l_fapi_rc, p8_cpu_special_wakeup , i_ex_target, i_operation , i_entity ); + if (l_fapi_rc) + { + FAPI_ERR("ERROR: p8_cpu_special_wakeup detected failed result"); + return l_fapi_rc; + } + + + + + return l_fapi_rc; + +} + + + //#ifdef FAPIECMD +} //end extern C +//#endif diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.H b/src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.H new file mode 100644 index 000000000..9583c227c --- /dev/null +++ b/src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.H @@ -0,0 +1,105 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/occ_procedures/proc_cpu_special_wakeup.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: proc_cpu_special_wakeup.H,v 1.8 2012/08/21 11:39:37 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cpu_special_wakeup.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_cpu_special_wakeup.H +// *! DESCRIPTION : Set the EX chiplet into Special Wake-up via one of the +// *! entity bits provided +// *! +// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com +// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_CPUSPECWKUP_H_ +#define _PROC_CPUSPECWKUP_H_ + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +#ifndef _PROC_SPCWKUP_ENTITY +#define _PROC_SPCWKUP_ENTITY +enum PROC_SPCWKUP_ENTITY +{ + HOST = 0X1, + FSP = 0x2, + OCC = 0x3, + PHYP = HOST + +}; + + +enum PROC_SPCWKUP_OPS +{ + SPCWKUP_ENABLE = 0x1, + SPCWKUP_DISABLE = 0x2 +}; + +#endif // _PROC_SPCWKUP_TGTS + + + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*proc_cpu_special_wakeup_FP_t) (const fapi::Target&, PROC_SPCWKUP_OPS , PROC_SPCWKUP_ENTITY ); + +extern "C" { + + + +//------------------------------------------------------------------------------ +// Parameter structure definitions +//------------------------------------------------------------------------------ + + + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// \param[in] i_target EX target +/// \param[in] i_entity Entity bit to use (OCC, PHYP, FSP) +/// \param[in] i_operation operation to use (SPCWKUP_ENABLE, SPCWKUP_DISABLE) + + +/// \retval ECMD_SUCCESS if something good happens, +/// \retval BAD_RETURN_CODE otherwise +fapi::ReturnCode +proc_cpu_special_wakeup(const fapi::Target& i_target, PROC_SPCWKUP_OPS i_operation , PROC_SPCWKUP_ENTITY i_entity ); + + +} // extern "C" + +#endif // _PROC_CPUSPECWKUP_H_ diff --git a/src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.C b/src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.C new file mode 100644 index 000000000..8aafead51 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.C @@ -0,0 +1,455 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: p8_pmc_force_vsafe.C,v 1.11 2013/04/01 04:16:44 stillgs Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_force_vsafe.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! OWNER NAME: Joe Procwriter Email: asmartpersion@xx.ibm.com +// *! +// *! General Description: Forces the PMC to VSAFE mode +// *! +// *! The purpose of this procedure is to ...... +// *! +// *! High-level procedure flow: +// *! o Do thing 1 +// *! o Do thing 2 +// *! o Do thing 3 +// *! o Check if all went well +// *! o If so celebrate +// *! o Else write logs, set bad return code +// *! +// *! Procedure Prereq: +// *! o System clocks are running +// *! +//------------------------------------------------------------------------------ + + +// ----------------------------------------------------------------------------- +// Flowchart Begins +// ----------------------------------------------------------------------------- +// ------------------ +// | Sim starts | +// ------------------ +// | +// | +// V +// Write a voltage value into +// PVSAFE - PMC_PARAMETER_REG1 +// Actually, this value will be been written outside this procedure by the OCC pstate installation routine after the p8_build_pstate runs to build +// the Pstate superstructure. We had identified a HWP ATTR (ATTR_PM_PVSAFE_PSTATE) to be used by p8_pmc_init to set this up originally but we're +// going away from that approach so that we have all things about Pstates being done in one place (the OCC pstate installation routine). +// So, this step should not exist in the p8_pmc_force_vsafe procedure; rather, you should write a value into the hardware with a script that +// represents what the OCC pstate install routine would have done + +// ------------------ +// | Procedure Starts | +// ------------------ +// | +// | +// V +// Write into PMC_OCC_HEARTBEAT_REG +// PMC_OCC_HEARTBEAT_TIME - Write the field to 0 to cause an immediate heartbeat loss. +// PMC_OCC_HEARTBEAT_EN - this bit needs to be 1 to acually cause the 0 time value to trigger the heartbeat loss. +// | +// | +// V +// POLL PMC_STATUS_REG (8) +// VOLT_CHG_ONGOING (bit 8) Yes... this bit needs to be 0 to indicate that the voltage controller is at its target. + +// 1.3V Turbo to 0.8V (most of the supported range) in 25mV steps (the eVRM step size with iVRMs enabled) is 20 steps which, at 12.5mV/5us rate +// (a modest time), yields 8us. Given this an error case, we need a conservative time. So let's set the timeout at 100us for the lab. +// To test the timeout, clear PMC.PMC_MODE_REG (3) (with a script) so that the PMC won't respond. + + + + +// Check that the other bits in PMC_STATUS_REG do not indicate errors (eg they should be all zeros). If any are 1 +// | ^ +// | | +// V | +// timeout ------ + +// ---------------------------------------------------------------------- +// Flowchart Ends +// ---------------------------------------------------------------------- + +// ---------------------------------------------------------------------- +// Includes +// ---------------------------------------------------------------------- +#include +#include "p8_scom_addresses.H" + +extern "C" { + +using namespace fapi; + +// ---------------------------------------------------------------------- +// Constant definitions +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Global variables +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function prototypes +// ---------------------------------------------------------------------- + + +// ---------------------------------------------------------------------- +// Function definitions +// ---------------------------------------------------------------------- + + +// function: xxx +/// \param[in] i_target Chip target +// returns: ECMD_SUCCESS if something good happens, +// BAD_RETURN_CODE otherwise +fapi::ReturnCode +p8_pmc_force_vsafe(const fapi::Target& i_target ) +{ + fapi::ReturnCode rc; + ecmdDataBufferBase data(64); + uint32_t e_rc = 0; + + // maximum number of status poll attempts to make before giving up + const uint32_t MAX_POLL_ATTEMPTS = 0x200; + + uint32_t count = 0; + // size_t i; + uint16_t pvsafe = 0; + bool l_set; + uint16_t pstate_target = 0; + uint16_t pstate_step_target = 0; + uint16_t pstate_actual = 0; + uint8_t DONE_FLAG = 0; + uint8_t any_error = 0; + uint8_t any_ongoing =0; + uint8_t dummy = 0; + uint8_t debug_mode = 1 ; + + FAPI_INF("Executing p8_pmc_force_vsafe ...."); + + // ****************************************************************** + // - PMC_MODE_REG checking + // ****************************************************************** + rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_MODE_REG_0x00062000) failed."); + return rc; + } + + + if ( (data.isBitClear(0) && data.isBitClear(1) )) + { + FAPI_ERR("PMC is not in HARDWARE or FIRMWARE AUCTION MODE"); + // FAPI_SET_HWP_ERROR(rc, RC_PROCPM_INITAL_AUCTION_MODE_ERR); + return rc; + } + + if ( ( data.isBitClear(3) )) + { + FAPI_ERR("PMC is disabled for Voltage changes"); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_VOLTAGE_CHAGE_MODE_ERR); + return rc; + } + + if ( ( !data.isBitClear(5) )) + { + FAPI_ERR("PMC is disabled PMC_MASTER_SEQUENCER"); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_MST_SEQUENCER_STATE_ERR); + return rc; + } + + // **************************************************************************** + // - PMC_STATE_MONITOR_AND_CTRL_REG PMC_PARAMETER_REG1 before the psafe + // **************************************************************************** + + rc = fapiGetScom(i_target, PMC_PARAMETER_REG1_0x00062006, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_PARAMETER_REG1_0x00062006) failed."); + return rc; + } + + e_rc = data.extractToRight( &pvsafe,22,8);if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + rc = fapiGetScom(i_target, PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002) failed."); + return rc; + } + + e_rc = data.extractToRight( &pstate_target,0,8);if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc = data.extractToRight( &pstate_step_target,8,8);if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc = data.extractToRight( &pstate_actual,16,8);if (e_rc) { rc.setEcmdError(e_rc); return rc; } + FAPI_INF(" voltage values before the hearbeat loss " ); + FAPI_INF(" pvsafe => %x , ptarget => %x , pstarget => %x ,pactual => %x " , pvsafe , pstate_target ,pstate_step_target , pstate_actual); + + // ****************************************************************** + // - SEE PMC_STATUS_REG if debug_mode ==1 + // ****************************************************************** + + if (debug_mode) + { + + rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + return rc; + } + FAPI_DBG(" debug_mode : status_b4_heartbeat_loss => 0x%16llx", data.getDoubleWord(0)); + + l_set = data.isBitSet(0); + FAPI_DBG(" pstate_processing_is_susp => %x ", l_set ) ; + l_set = data.isBitSet(1); + FAPI_DBG(" gpsa_bdcst_error => %x ", l_set ); + + e_rc = data.extractToRight( &dummy,2,3);if (e_rc) { rc.setEcmdError(e_rc); return rc; } + FAPI_DBG(" gpsa_bdcst_resp_info => %x ", dummy ); + // l_set = data.isBitSet(2); + // FAPI_DBG(" gpsa_bdcst_resp_dbgo => %x ", l_set ); + l_set = data.isBitSet(5); + FAPI_DBG(" gpsa_vchg_error => %x ", l_set ); + l_set = data.isBitSet(6); + FAPI_DBG(" gpsa_timeout_error => %x ", l_set ); + l_set = data.isBitSet(7); + FAPI_DBG(" gpsa_chg_ongoing => %x ", l_set ); + l_set = data.isBitSet(8); + FAPI_DBG(" volt_chg_ongoing => %x ", l_set ); + l_set = data.isBitSet(9); + FAPI_DBG(" brd_cst_ongoing => %x ", l_set ); + l_set = data.isBitSet(10); + FAPI_DBG(" gpsa_table_error => %x ", l_set ); + l_set = data.isBitSet(11); + FAPI_DBG(" pstate_interchip_error => %x ", l_set ); + l_set = data.isBitSet(12); + FAPI_DBG(" istate_processing_is_susp => %x ", l_set ); + + } // if(debug_mode) + + // ****************************************************************** + // - PMC_OCC_HEARTBEAT_REG + // ****************************************************************** + + FAPI_INF("Forcing PMC Heartbeat loss "); + + e_rc = data.flushTo0(); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + e_rc = data.setBit(16); if (e_rc) { rc.setEcmdError(e_rc); return rc; } + + rc = fapiPutScom(i_target, PMC_OCC_HEARTBEAT_REG_0x00062066, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_OCC_HEARTBEAT_REG_0x00062066) failed."); return rc; + } + + rc = fapiPutScom(i_target, PMC_OCC_HEARTBEAT_REG_0x00062066, data ); + if (rc) + { + FAPI_ERR("fapiPutScom(PMC_OCC_HEARTBEAT_REG_0x00062066) failed."); return rc; + } + + // \todo check with Thomas B. on how immediate the on-going will assert. + // This delay may be covered under the "fapiGetScom" operation. + // rc = fapiDelay(); + DONE_FLAG = 0; + + // ****************************************************************** + // POLL for PMC_STATUS_REG --> BIT_8 to go to 0 or any errors + // ****************************************************************** + FAPI_DBG("Start polling for ongoing to go low ... "); + // Loop only if count is less thean poll attempts and DONE_FLAG = 0 and no error + for(count=0 , DONE_FLAG = 0 , any_error = 0; count<=MAX_POLL_ATTEMPTS && DONE_FLAG == 0 && any_error == 0; count++) + { + rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); + return rc; + } + + FAPI_DBG(" poll_status => 0x%16llx", data.getDoubleWord(0)); + /* any_error = !(data.isBitClear(0) && data.isBitClear(1) && data.isBitClear(5) && + data.isBitClear(6) && data.isBitClear(10) && data.isBitClear(11) && + data.isBitClear(12)); + */ + any_error = !(data.isBitClear(1) && data.isBitClear(5) && + data.isBitClear(6) && data.isBitClear(10) && data.isBitClear(11) && + data.isBitClear(12)); + any_ongoing = !(data.isBitClear(8) && data.isBitClear(7)&& data.isBitClear(9)); + // Check for voltage change has any error + if ( any_error == 1) + { + // An error was detected + + // \todo These messages will fail in HostBoot as genHexRightStr + // cannot be used. + // Suggest doing a walking bit check (if (isBitSet(x))) to write + // which bits are on + // FAPI_DBG(" -----------------------------------------------------"); + FAPI_DBG(" PMC_STATUS_REG is Read after the opn ----------> "); + // FAPI_DBG(" -----------------------------------------------------"); + + l_set = data.isBitSet(0); + FAPI_ERR(" pstate_processing_is_susp => %x ", l_set ) ; + l_set = data.isBitSet(1); + FAPI_ERR(" gpsa_bdcst_error => %x ", l_set ); + + e_rc = data.extractToRight( &dummy,2,3);if (e_rc) { rc.setEcmdError(e_rc); return rc; } + FAPI_ERR(" gpsa_bdcst_resp_info => %x ", dummy ); + // l_set = data.isBitSet(2); + // FAPI_ERR(" gpsa_bdcst_resp_dbgo => %x ", l_set ); + l_set = data.isBitSet(5); + FAPI_ERR(" gpsa_vchg_error => %x ", l_set ); + l_set = data.isBitSet(6); + FAPI_ERR(" gpsa_timeout_error => %x ", l_set ); + l_set = data.isBitSet(7); + FAPI_ERR(" gpsa_chg_ongoing => %x ", l_set ); + l_set = data.isBitSet(8); + FAPI_ERR(" volt_chg_ongoing => %x ", l_set ); + l_set = data.isBitSet(9); + FAPI_ERR(" brd_cst_ongoing => %x ", l_set ); + l_set = data.isBitSet(10); + FAPI_ERR(" gpsa_table_error => %x ", l_set ); + l_set = data.isBitSet(11); + FAPI_ERR(" pstate_interchip_error => %x ", l_set ); + l_set = data.isBitSet(12); + FAPI_ERR(" istate_processing_is_susp => %x ", l_set ); + + // FAPI_DBG(" -----------------------------------------------------"); + + FAPI_ERR("Error detected with PMC on-going deassertion during safe voltage movement "); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_VLT_ERROR); + return rc; + + } // end of error if + else if (any_ongoing == 0) + { + // Voltage change done (not on-going) and not errors + + // \todo Check that PVSAFE Pstate (in PMC Parameter Reg1) is the value + // in the voltage stepper in the following fields of + // PMC_STATE_MONITOR_AND_CRTL_REG + // 0:7 - Global Pstate Target + // 8:15 - Global Pstate Step Target + // 16:23 - Global Pstate Actual + // if the above do not match, post an error + + FAPI_DBG(" status_after_heartbeat_loss => 0x%16llx", data.getDoubleWord(0)); + + l_set = data.isBitSet(0); + FAPI_DBG(" pstate_processing_is_susp => %x ", l_set ) ; + l_set = data.isBitSet(1); + FAPI_DBG(" gpsa_bdcst_error => %x ", l_set ); + + e_rc = data.extractToRight( &dummy,2,3);if (e_rc) { rc.setEcmdError(e_rc); return rc; } + FAPI_DBG(" gpsa_bdcst_resp_info => %x ", dummy ); + + l_set = data.isBitSet(5); + FAPI_DBG(" gpsa_vchg_error => %x ", l_set ); + l_set = data.isBitSet(6); + FAPI_DBG(" gpsa_timeout_error => %x ", l_set ); + l_set = data.isBitSet(7); + FAPI_DBG(" gpsa_chg_ongoing => %x ", l_set ); + l_set = data.isBitSet(8); + FAPI_DBG(" volt_chg_ongoing => %x ", l_set ); + l_set = data.isBitSet(9); + FAPI_DBG(" brd_cst_ongoing => %x ", l_set ); + l_set = data.isBitSet(10); + FAPI_DBG(" gpsa_table_error => %x ", l_set ); + l_set = data.isBitSet(11); + FAPI_DBG(" pstate_interchip_error => %x ", l_set ); + l_set = data.isBitSet(12); + FAPI_DBG(" istate_processing_is_susp => %x ", l_set ); + + FAPI_DBG("Voltage_change done without any error ... "); + rc = fapiGetScom(i_target, PMC_PARAMETER_REG1_0x00062006, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_PARAMETER_REG1_0x00062006) failed."); + return rc; + } + + e_rc = data.extractToRight( &pvsafe,22,8); + if (e_rc) {rc.setEcmdError(e_rc); return rc; } + + rc = fapiGetScom(i_target, PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002, data ); + if (rc) + { + FAPI_ERR("fapiGetScom(PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002) failed."); + return rc; + } + + e_rc = data.extractToRight( &pstate_target,0,8); + e_rc = data.extractToRight( &pstate_step_target,8,8); + e_rc = data.extractToRight( &pstate_actual,16,8); + if (e_rc) + { + rc.setEcmdError(e_rc); + return rc; + } + FAPI_INF(" pvsafe => %x , ptarget => %x , pstarget => %x ,pactual => %x " , pvsafe , pstate_target ,pstate_step_target , pstate_actual); + + if (pstate_target != pvsafe || pstate_step_target != pvsafe || pstate_actual != pvsafe ) + { + FAPI_ERR("Pstate monitor and control register targets didnot match"); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PSTATE_MONITOR_ERR); + return rc; + } + DONE_FLAG = 1; + } + else // voltage change is ongoing so wait and then poll again + { + FAPI_DBG(" status => 0x%16llx", data.getDoubleWord(0)); + + // wait for 1 millisecond in hardware, 1000 cycles in sim + rc = fapiDelay(1000*1000, 20000000); + if (rc) + { + FAPI_ERR("fapi delay ends up with error"); + return rc ; + } + } + } // For loop + + // If we get here, the above loop timed out + if (count>=MAX_POLL_ATTEMPTS) + { + FAPI_ERR("Timed out wait for voltage change on-going to drop"); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_VLT_TIMEOUT); + return rc; + } + // simcheckpoint("pcn_o2s_poll_status_12"); + + return rc ; +} // Procedure + +} //end extern C diff --git a/src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.H b/src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.H new file mode 100755 index 000000000..00d9207d6 --- /dev/null +++ b/src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.H @@ -0,0 +1,76 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/occ/p8_pmc_force_vsafe.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: p8_pmc_force_vsafe.H,v 1.2 2012/09/17 14:00:00 pchatnah Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_force_vsafe.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : p8_pmc_force_vsafe.H +// *! DESCRIPTION : Force Safe voltage to the chip via PMC +// *! +// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com +// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode (*p8_pmc_force_vsafe_FP_t) (const fapi::Target& ); + +extern "C" { + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + + + +//------------------------------------------------------------------------------ +// Parameter structure definitions +//------------------------------------------------------------------------------ + + + +//------------------------------------------------------------------------------ +// Function prototype +//------------------------------------------------------------------------------ +/// \param[in] i_target Chip target + +/// \retval ECMD_SUCCESS if something good happens, +/// \retval BAD_RETURN_CODE otherwise +fapi::ReturnCode +p8_pmc_force_vsafe(const fapi::Target& i_target ); + + +} // extern "C" + + diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_pm_prep_for_reset_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_pm_prep_for_reset_errors.xml index 10b0e91d6..f7c26cd96 100644 --- a/src/usr/hwpf/hwp/runtime_errors/p8_pm_prep_for_reset_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/p8_pm_prep_for_reset_errors.xml @@ -5,7 +5,7 @@ - + @@ -20,9 +20,16 @@ + + + RC_PROCPM_PREP_TARGET_ERR + Errors in Targets passed -- PM_RESET-MODE + + + RC_PROCPM_PREP_CODE_PROC_OCC Errors in proc_occ_control.C -- PM_RESET-MODE -- cgit v1.2.1