From d42232139a2463453024d37a28e202b821bef13a Mon Sep 17 00:00:00 2001 From: Benjamin Weisenbeck Date: Tue, 7 Jun 2016 08:56:07 -0500 Subject: PRD: PLL Analysis Change-Id: I2d8396e867c45a729f8d947411add95ddd310e2d RTC: 136052 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25574 Tested-by: Jenkins Server Reviewed-by: Caleb N. Palmer Reviewed-by: Daniel M. Crowell Reviewed-by: Zane C. Shelley Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27139 Tested-by: FSP CI Jenkins --- src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) (limited to 'src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C') diff --git a/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C b/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C index 9e28f7a00..6316694fc 100755 --- a/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C +++ b/src/usr/diag/prdf/common/plat/p9/prdfP9Configurator.C @@ -253,8 +253,8 @@ errlHndl_t PlatConfigurator::addDomainChips( TARGETING::TYPE i_type, i_type ); } - // Generic empty PLL domain maps, if they are used. - PllDomainMap pllDmnMap1, pllDmnMap2; + // Generic empty PLL domain map + PllDomainMap pllDmnMap; // Add each chip to the chip domain. for ( const auto & trgt : trgtList ) @@ -276,16 +276,13 @@ errlHndl_t PlatConfigurator::addDomainChips( TARGETING::TYPE i_type, switch ( i_type ) { case TYPE_PROC: - addChipToPllDomain( CLOCK_DOMAIN_FAB, pllDmnMap1, + addChipToPllDomain( CLOCK_DOMAIN_FAB, pllDmnMap, chip, trgt, TYPE_PROC, scanFac, resFac ); - addChipToPllDomain( CLOCK_DOMAIN_IO, pllDmnMap2, - chip, trgt, TYPE_PCI, - scanFac, resFac ); break; case TYPE_MEMBUF: - addChipToPllDomain( CLOCK_DOMAIN_MEMBUF, pllDmnMap1, + addChipToPllDomain( CLOCK_DOMAIN_MEMBUF, pllDmnMap, chip, trgt, TYPE_MEMBUF, scanFac, resFac ); break; @@ -295,8 +292,7 @@ errlHndl_t PlatConfigurator::addDomainChips( TARGETING::TYPE i_type, } // Add the PLL domain maps to the PLL domain map list. - if ( !pllDmnMap1.empty() ) io_pllDmnLst.push_back( pllDmnMap1 ); - if ( !pllDmnMap2.empty() ) io_pllDmnLst.push_back( pllDmnMap2 ); + if ( !pllDmnMap.empty() ) io_pllDmnLst.push_back( pllDmnMap ); // Flush rule table cache since objects are all built. Prdr::LoadChipCache::flushCache(); @@ -315,7 +311,7 @@ void PlatConfigurator::addChipToPllDomain( DOMAIN_ID i_domainId, ScanFacility & i_scanFac, ResolutionFactory & i_resFac ) { - // TODO: RTC 136052 - The position used here should be based on clock + // TODO: RTC 155673 - The position used here should be based on clock // domains. In the past there happened to be one clock source for each // node. In which case, we just used the node position. Unfortunately, // that is not very maintainable code. Instead, we should be querying @@ -347,7 +343,7 @@ void PlatConfigurator::addPllDomainsToSystem( const PllDomainMapList & i_list ) lit != i_list.end(); ++lit ) { for ( PllDomainMap::const_iterator mit = lit->begin(); - mit != lit->begin(); ++mit ) + mit != lit->end(); ++mit ) { sysDmnLst.push_back( mit->second ); } -- cgit v1.2.1