From 025298b52002867f1e3516ba9810fd4642262980 Mon Sep 17 00:00:00 2001 From: Andrew Geissler Date: Tue, 26 Jul 2016 14:21:15 -0500 Subject: Updates for new scratch registers in P9 P9 moves us from 8 scratch registers to 4. This commit handles this change and also adds the base support for partial cache. Change-Id: Ibe050c663744285dd3e77850649236a669dadbd6 RTC: 150923 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27462 Reviewed-by: Christian R. Geddes Tested-by: Jenkins Server Reviewed-by: Martin Gloff Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell Reviewed-by: William G. Hoffa --- src/lib/syscall_mmio.C | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/lib') diff --git a/src/lib/syscall_mmio.C b/src/lib/syscall_mmio.C index 1a0de8a9f..f7bce955b 100644 --- a/src/lib/syscall_mmio.C +++ b/src/lib/syscall_mmio.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2010,2015 */ +/* Contributors Listed Below - COPYRIGHT 2010,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -66,18 +66,19 @@ void mmio_hmer_write(uint64_t value) */ static uint64_t mmio_scratch_base() { - // @todo-RTC:130438 Verify value for P9 ProcessorCoreType cpuType = CpuID::getCpuType(); switch (cpuType) { case CORE_POWER8_MURANO: case CORE_POWER8_VENICE: case CORE_POWER8_NAPLES: + return 0x40; case CORE_POWER9_NIMBUS: case CORE_POWER9_CUMULUS: case CORE_UNKNOWN: default: - return 0x40; + // See misc.C - updateScratchReg() for more info on this + return 0x00; } } /** Global cache of the scratch register SPRC base address. */ -- cgit v1.2.1