From 4638dc513da1390ce3652f34c51f39ac454e8953 Mon Sep 17 00:00:00 2001 From: Dan Crowell Date: Tue, 17 Dec 2019 15:40:48 -0600 Subject: Add current istep into TI SRC Word4 of the SRC is defined to be the 'last progress code' for FSP SRCs. For Hostboot TIs, we currently leave that word zero. This change will add the same data that we put into the scratch register 5 into word4 so that we will have the failing istep for any TI we encounter. Change-Id: Iaf5ec835d45b1ea3a6ced20b5b7f7d07216c548e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88813 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Ilya Smirnov Reviewed-by: Matt Derksen Reviewed-by: Nicholas E Bofferding --- src/kernel/terminate.C | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'src/kernel') diff --git a/src/kernel/terminate.C b/src/kernel/terminate.C index cb70e9be6..fb3e1d069 100644 --- a/src/kernel/terminate.C +++ b/src/kernel/terminate.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2018 */ +/* Contributors Listed Below - COPYRIGHT 2012,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -128,4 +128,13 @@ void termSetHbDump(void) return; } + +void termSetIstep(uint32_t i_istep) +{ + // Set istep into progress code word of the SRC + kernel_TIDataArea.src.SRCword4 = i_istep; + return; +} + + #endif // BOOTLOADER -- cgit v1.2.1