From 59a63d52bee3c84b60cd04c2128ca8786e7e9035 Mon Sep 17 00:00:00 2001 From: Patrick Williams Date: Tue, 14 Aug 2012 12:15:47 -0500 Subject: Ensure PHYP thread order is correct. * Choose thread with the lowest PIR as the last to enter payload. * Use HRMOR update process from Murano Book IV. RTC: 43166 Change-Id: I629f4a55cba1967a13c31a16095697b7142ca407 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1529 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III --- src/kernel/misc.C | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) (limited to 'src/kernel/misc.C') diff --git a/src/kernel/misc.C b/src/kernel/misc.C index d45473259..a928849fb 100644 --- a/src/kernel/misc.C +++ b/src/kernel/misc.C @@ -29,7 +29,8 @@ #include #include -extern "C" void kernel_shutdown(size_t, uint64_t, uint64_t) NO_RETURN; +extern "C" + void kernel_shutdown(size_t, uint64_t, uint64_t, uint64_t) NO_RETURN; namespace KernelMisc @@ -98,6 +99,7 @@ namespace KernelMisc else { static Barrier* l_barrier = new Barrier(CpuManager::getCpuCount()); + static uint64_t l_lowestPIR = 0xffffffffffffffffull; if (c->master) { @@ -105,11 +107,31 @@ namespace KernelMisc g_payload_base, g_payload_entry); } + // Need to identify the thread with the lowest PIR because it needs + // to be the last one to jump to PHYP. + uint64_t l_pir = getPIR(); + do + { + uint64_t currentPIR = l_lowestPIR; + if (l_pir > currentPIR) + { + break; + } + + if (__sync_bool_compare_and_swap(&l_lowestPIR, + currentPIR, l_pir)) + { + break; + } + + } while(1); + l_barrier->wait(); kernel_shutdown(CpuManager::getCpuCount(), g_payload_base, - g_payload_entry); + g_payload_entry, + l_lowestPIR); } } -- cgit v1.2.3