From c1d3f833fa86a6f2e66a170992d6263f4742c122 Mon Sep 17 00:00:00 2001 From: Adam Muhle Date: Wed, 2 Jan 2013 16:16:56 -0600 Subject: Improve PNOR DD Micron NOR Workaround Improving the workaround implemented in Story 53201 to be more efficient. Changing to use the normal SFC polling to determine when the write/erase operations are complete and then reading the Micron Flag Status register once to keep the chip from getting into a bad state. This should reduce the traffic on the SPI bus. Change-Id: I315b165bcd3014a2c3121fd97594e73a2e6c1082 RTC: 61064 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2795 Tested-by: Jenkins Server Reviewed-by: Douglas R. Gilbert Reviewed-by: Daniel M. Crowell Reviewed-by: A. Patrick Williams III --- src/include/usr/pnor/pnor_reasoncodes.H | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/include') diff --git a/src/include/usr/pnor/pnor_reasoncodes.H b/src/include/usr/pnor/pnor_reasoncodes.H index a5b321b66..e8ad6341d 100644 --- a/src/include/usr/pnor/pnor_reasoncodes.H +++ b/src/include/usr/pnor/pnor_reasoncodes.H @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2011,2012 */ +/* COPYRIGHT International Business Machines Corp. 2011,2013 */ /* */ /* p1 */ /* */ @@ -49,8 +49,7 @@ namespace PNOR MOD_PNORDD_READLPC = 0x18, /**< pnordd.C : PnorDD::readLPC */ MOD_PNORDD_WRITELPC = 0x19, /**< pnordd.C : PnorDD::writeLPC */ MOD_PNORDD_ERASEFLASH = 0x1A, /**< pnordd.C : PnorDD::eraseFlash */ - MOD_PNORDD_COMPAREANDWRITEBLOCK = 0x1B, /**< pnordd.C : PnorDD::compareAndWriteBlock */ - MOD_PNORDD_MICRONOPCOMPLETE = 0x1C, /**< pnordd.C : PnorDD::micronOpComplete */ + MOD_PNORDD_MICRONFLAGSTATUS = 0x1B, /**< pnordd.C : PnorDD::micronFlagStatus */ }; -- cgit v1.2.1