From 1cee7cd499df2521027dacef1f03375688db935c Mon Sep 17 00:00:00 2001 From: Ilya Smirnov Date: Fri, 15 Nov 2019 16:57:52 -0600 Subject: Fix UVBWLIST SBE Chip Op The address where SBE is to populate the ultravisor white/blacklist is to be put in Mbox reg1, which means that the register needs to be masked in the command we're sending. Before this change, only Mbox reg0 was masked, and SBE was not getting the correct address at which to populate the UVBWLIST. This change masks Mbox Reg 1 so that SBE can receive the correct address for the UVBWLIST. Change-Id: I841db74dc407f51c14f005b9ccd457d5641ffa7e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87102 Reviewed-by: Nicholas E Bofferding Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Reviewed-by: RAJA DAS Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell --- src/include/usr/sbeio/sbe_psudd.H | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/include') diff --git a/src/include/usr/sbeio/sbe_psudd.H b/src/include/usr/sbeio/sbe_psudd.H index 3a21ad122..688c9086b 100644 --- a/src/include/usr/sbeio/sbe_psudd.H +++ b/src/include/usr/sbeio/sbe_psudd.H @@ -338,7 +338,7 @@ class SbePsu */ enum psuSecurityListBinDumpNonReservedMsgs { - SBE_SECURITY_LIST_BIN_DUMP_REQ_USED_REGS = 0x01, + SBE_SECURITY_LIST_BIN_DUMP_REQ_USED_REGS = 0x03, SBE_SECURITY_LIST_BIN_DUMP_RSP_USED_REGS = 0x01, }; -- cgit v1.2.1