From 97bd69daf028bec2f7d7f4fbd8feb49486fb4577 Mon Sep 17 00:00:00 2001 From: Dean Sanner Date: Thu, 3 Jan 2013 10:16:18 -0600 Subject: Basic devtree support Simple devtree support for Sapphire in SPless mode Change-Id: I4a70bfc5cd3eb3dbd1b443869c046c789f98cc95 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3739 Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell Reviewed-by: A. Patrick Williams III --- src/include/usr/intr/interrupt.H | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'src/include/usr/intr') diff --git a/src/include/usr/intr/interrupt.H b/src/include/usr/intr/interrupt.H index cf129712a..f41f8ccf6 100644 --- a/src/include/usr/intr/interrupt.H +++ b/src/include/usr/intr/interrupt.H @@ -33,6 +33,37 @@ namespace TARGETING namespace INTR { + /** + * cpu PIR register + */ + struct PIR_t + { + union + { + uint32_t word; + struct + { + //P8: + uint32_t reserved:19; //!< zeros + uint32_t nodeId:3; //!< node (0-3) + uint32_t chipId:3; //!< chip pos on node (0-5) + uint32_t coreId:4; //!< Core number (1-6,9-14)? + uint32_t threadId:3; //!< Thread number (0-7) + } PACKED; + }; + PIR_t(uint32_t i_word = 0) : word(i_word) {} + + PIR_t operator= (uint32_t i_word) + { + word = i_word; + return word; + } + + bool operator< (const PIR_t& r) const + { + return word < r.word; + } + }; /** * External Interrupt Types (XISR) @@ -165,6 +196,15 @@ namespace INTR */ errlHndl_t enablePsiIntr(TARGETING::Target * i_target); + /** + * Return the interrupt presenter for requested target/thread + * @param[in] i_ex The target EX + * @param[in] i_thread Which thread on EX (0-7) + * @return 64 bit address for the interrupt present addr + */ + uint64_t getIntpAddr(const TARGETING::Target * i_ex, + uint8_t i_thread); + }; #endif -- cgit v1.2.1