From 890759122216b1bff2f31de63d6974deafa48ce7 Mon Sep 17 00:00:00 2001 From: Andre Marin Date: Wed, 2 Nov 2016 14:55:16 -0500 Subject: Add LRDIMM to translation register infrastructure and unit tests. Fix row # for different SDRAM densities in dimm::kind. Created functions for common patterns to facilitate the creation of common debug print statements. This helps create unit tests debugibility and assures that the correct bits are being set. Change-Id: If1d2fa8b823a386469e1605cb4744451cf1ad6b9 Original-Change-Id: I36ea2ba8bfc299f6c69a0d744c4caf2436e37f14 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32150 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Louis Stermole Reviewed-by: JACOB L. HARVEY Reviewed-by: Christian R. Geddes Reviewed-by: STEPHEN GLANCY Reviewed-by: Brian R. Silver Reviewed-by: Matt K. Light Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37409 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell --- .../chips/p9/procedures/hwp/memory/lib/mc/xlate.C | 1215 +++++++++++++------- .../chips/p9/procedures/hwp/memory/lib/mc/xlate.H | 768 ++++++++++--- 2 files changed, 1361 insertions(+), 622 deletions(-) (limited to 'src/import') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index fdb92513d..05c8ac95e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -59,202 +59,452 @@ static const std::vector xlate_map = { // 1R 4Gbx4 DDR4 RDIMM { - dimm::kind(1, 1, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 8), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_8GB), xlate_dimm_1R1T4Gbx4 }, // 1R 8Gbx4 DDR4 RDIMM { - dimm::kind(1, 1, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 16), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_16GB), xlate_dimm_1R1T8Gbx4 }, // 1R 16Gbx4 DDR4 RDIMM { - dimm::kind(1, 1, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 32), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), xlate_dimm_1R1T16Gbx4 }, // 2R 4Gbx4 DDR4 RDIMM { - dimm::kind(2, 2, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 16), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_16GB), xlate_dimm_2R2T4Gbx4 }, // 2R 8Gbx4 DDR4 RDIMM { - dimm::kind(2, 2, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 32), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), xlate_dimm_2R2T8Gbx4 }, // 2R 16Gbx4 DDR4 RDIMM { - dimm::kind(2, 2, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 64), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), xlate_dimm_2R2T16Gbx4 }, // 4R 4Gbx4 DDR4 RDIMM { - dimm::kind(4, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 32), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), xlate_dimm_4R4T4Gbx4 }, // 4R 8Gbx4 DDR4 RDIMM { - dimm::kind(4, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 64), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), xlate_dimm_4R4T8Gbx4 }, // 4R 16Gbx4 DDR4 RDIMM { - dimm::kind(4, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 128), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB), xlate_dimm_4R4T16Gbx4 }, // - // 3DS + // 3DS RDIMM // // 1R 2H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(1, 2, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 16), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_16GB), xlate_dimm_1R2T4Gbx4 }, // 1R 2H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(1, 2, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 32), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), xlate_dimm_1R2T8Gbx4 }, // 1R 2H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(1, 2, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 64), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), xlate_dimm_1R2T16Gbx4 }, // 1R 4H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(1, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 32), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), xlate_dimm_1R4T4Gbx4 }, // 1R 4H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(1, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 64), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), xlate_dimm_1R4T8Gbx4 }, // 1R 4H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(1, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 128), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB), xlate_dimm_1R4T16Gbx4 }, // 1R 8H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(1, 8, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 64), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), xlate_dimm_1R8T4Gbx4 }, // 1R 8H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(1, 8, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 128), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB), xlate_dimm_1R8T8Gbx4 }, // 1R 8H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(1, 8, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 256), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_256GB), xlate_dimm_1R8T16Gbx4 }, // 2R 2H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(2, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 32), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), xlate_dimm_2R4T4Gbx4 }, // 2R 2H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(2, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 64), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), xlate_dimm_2R4T8Gbx4 }, // 2R 2H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(2, 4, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 128), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB), xlate_dimm_2R4T16Gbx4 }, // 2R 4H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(2, 8, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 64), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), xlate_dimm_2R8T4Gbx4 }, // 2R 4H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(2, 8, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 128), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB), xlate_dimm_2R8T8Gbx4 }, // 2R 4H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(2, 8, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 256), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_256GB), xlate_dimm_2R8T16Gbx4 }, // 2R 8H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(2, 16, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 128), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM16, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB), xlate_dimm_2R16T4Gbx4 }, // 2R 8H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(2, 16, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 256), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_256GB), xlate_dimm_2R16T8Gbx4 }, // 2R 8H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(2, 16, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 16, 512), + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_512GB), xlate_dimm_2R16T16Gbx4 }, + + + // + // LRDIMM + // + + // 2R 8Gbx4 32GB DDR4 LRDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB), + xlate_dimm_2R2T8Gbx4 + }, + + // 4R 8Gbx4 64GB DDR4 LRDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), + xlate_dimm_4R4T8Gbx4 + }, + + // + // 3DS LRDIMM + // + + // 2R 2H 3DS 8Gbx4 64GB DDR4 LRDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_64GB), + xlate_dimm_2R4T8Gbx4 + }, + + // 2R 4H 3DS 8Gbx4 64GB DDR4 LRDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM17, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB), + xlate_dimm_2R8T8Gbx4 + }, + + // 2R 2H 3DS 16Gbx4 128GB DDR4 LRDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_128GB), + xlate_dimm_2R4T16Gbx4 + }, + + // 2R 4H 3DS 16Gbx4 256GB DDR4 LRDIMM + { + dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, + fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, + fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, + fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, + fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + fapi2::ENUM_ATTR_EFF_DRAM_ROW_BITS_NUM18, + fapi2::ENUM_ATTR_EFF_DIMM_SIZE_256GB), + xlate_dimm_2R8T16Gbx4 + }, + }; /// @@ -343,6 +593,10 @@ static void column_and_16bank_helper(fapi2::buffer& io_xlate1, fapi2:: io_xlate2.insertFromRight(BG1_MAP); + + FAPI_DBG("Set bits for column and 16 banks. MCP0XLT1: 0x%016lx, MCP0XLT2: 0x%016lx", + uint64_t(io_xlate1), uint64_t(io_xlate2) ); + } /// @@ -354,21 +608,30 @@ static void column_and_16bank_helper(fapi2::buffer& io_xlate1, fapi2:: /// @param[in] i_offset, which side of the register to setup /// @param[in] i_map the place to map the D bit in the register /// @param[in,out] io_xlate the translation register +/// @return FAPI2_RC_SUCCESS iff okay /// -static void d_bit_helper( const fapi2::Target& i_target, - const bool i_largest, - const uint64_t i_offset, - const uint64_t i_map, - fapi2::buffer& io_xlate0) +static fapi2::ReturnCode d_bit_helper( const fapi2::Target& i_target, + const bool i_largest, + const uint64_t i_offset, + const uint64_t i_map, + fapi2::buffer& io_xlate0) { - // Setup the D-bit. If we're the largest DIMM, it is our mapping which maters. + // Setup the D-bit. If we're the largest DIMM, it is our mapping which matters. // Notice that we don't care if the D-value bit has been set; this mapping needs to be setup regardless // (SJ Powell says so) if (i_largest) { - FAPI_INF("setting d-bit mapping (am largest) 0x%x for %s", i_map, mss::c_str(i_target)); - io_xlate0.insertFromRight(i_map, MCS_PORT02_MCP0XLT0_D_BIT_MAP + i_offset, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN); + FAPI_INF("setting d-bit mapping (am largest) 0x%x at start: %d, len: %d for %s", + i_map, MCS_PORT02_MCP0XLT0_D_BIT_MAP + i_offset, MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN, mss::c_str(i_target)); + + FAPI_TRY( io_xlate0.insertFromRight(i_map, MCS_PORT02_MCP0XLT0_D_BIT_MAP + i_offset, + MCS_PORT02_MCP0XLT0_D_BIT_MAP_LEN) ); } + + FAPI_DBG("d-bit %s set. MCP0XLT0: 0x%016lx", (i_largest == true ? "was" : "was NOT"), uint64_t(io_xlate0)); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -380,13 +643,14 @@ static void d_bit_helper( const fapi2::Target& i_target, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t M1_MAP(0b01111); constexpr uint64_t R15_MAP(0b00110); @@ -394,23 +658,25 @@ void xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, // Set the proper bit if there is a DIMM in this slot. If there wasn't, we wouldn't see // this DIMM in the vector, so this is always safe. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_VALID + i_offset); + FAPI_TRY(set_xlate_dimm_slot(i_offset, io_xlate0) ); // Check our master ranks, and enable the proper bits. // Note this seems a little backward. M0 is the left most bit, M1 the right most. // So, M1 changes for ranks 0,1 and M0 changes for ranks 3,4 // 2 rank DIMM, so master bit 1 (least significant) bit needs to be mapped. - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID + i_offset); - io_xlate0.insertFromRight(M1_MAP); + FAPI_TRY( set_xlate_mrank(M1_MAP, i_offset, io_xlate0) ); // Tell the MC which of the row bits are valid, and map the DIMM selector // We're a 16 row DIMM, so ROW15 is valid. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + i_offset); - io_xlate0.insertFromRight(R15_MAP); + FAPI_TRY( set_xlate_row(R15_MAP, i_offset, io_xlate0) ); // Drop down the column assignments column_and_16bank_helper(io_xlate1, io_xlate2); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } @@ -423,13 +689,14 @@ void xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 8Gbx4 DDR4 RDIMM -/// -void xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP(0b00101); constexpr uint64_t DBIT_MAP(0b00100); @@ -440,12 +707,14 @@ void xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, // Tell the MC which of the row bits are valid, and map the DIMM selector // We're a 17 row DIMM, so ROW16 is valid. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(R16_MAP); + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); // Column assignments happened when we called xlate_dimm_2R2T4Gbx4 - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -457,29 +726,32 @@ void xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R17_MAP(0b00100); constexpr uint64_t DBIT_MAP(0b00011); // We're basically a 2R 8Gbx4 with an extra row. So lets setup like we're one of those, // add row 16 and shift the D bit as needed. - xlate_dimm_2R2T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R2T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); // Tell the MC which of the row bits are valid, and map the DIMM selector // We're a 18 row DIMM, so ROW17 is valid. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(R17_MAP); + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); // Column assignments happened when we called xlate_dimm_2R2T8Gbx4 - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -491,26 +763,26 @@ void xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 2H 3DS 4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { - constexpr uint64_t CLEAR_MAP(0b00000); constexpr uint64_t M1_MAP(0b00110); // We're just like a 1R 4H 4Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_1R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - io_xlate0.clearBit(MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID + i_offset); - io_xlate1.insertFromRight(CLEAR_MAP); + clear_xlate_srank(i_offset, io_xlate0, io_xlate1); - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID + i_offset); - io_xlate0.insertFromRight(M1_MAP); + FAPI_TRY( set_xlate_mrank(M1_MAP, i_offset, io_xlate0) ); +fapi_try_exit: + return fapi2::current_err; } /// @@ -522,25 +794,28 @@ void xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 2H 3DS 8Gbx4 DDR4 RDIMM -/// -void xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP(0b00100); constexpr uint64_t DBIT_MAP(0b00011); // We're just like a 2R 2H 4Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_2R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // Add in Row 16 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(R16_MAP); + // We're a 17 row DIMM, so ROW16 is valid. + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -552,25 +827,28 @@ void xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 2H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R17_MAP(0b00011); constexpr uint64_t DBIT_MAP(0b00010); // We're just like a 2R 2H 8Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_2R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // Add in Row 17 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(R17_MAP); + // We're a 18 row DIMM, so ROW17 is valid. + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -582,25 +860,26 @@ void xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 4H 3DS 4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { - constexpr uint64_t CLEAR_MAP(0b00000); constexpr uint64_t M1_MAP(0b00101); // We're just like a 1R 8H 4Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_1R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + + clear_xlate_srank(i_offset, io_xlate0, io_xlate1); - io_xlate0.clearBit(MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID + i_offset); - io_xlate1.insertFromRight(CLEAR_MAP); + FAPI_TRY( set_xlate_mrank(M1_MAP, i_offset, io_xlate0) ); - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID + i_offset); - io_xlate0.insertFromRight(M1_MAP); +fapi_try_exit: + return fapi2::current_err; } /// @@ -612,25 +891,28 @@ void xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 4H 3DS 8Gbx4 DDR4 RDIMM -/// -void xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP(0b00011); constexpr uint64_t DBIT_MAP(0b00010); // We're just like a 2R 4H 3DS 4Gbx4 so lets start there and modify - xlate_dimm_2R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + + // We're a 17 row DIMM, so ROW16 is valid. + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); - // Add in Row 16 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(R16_MAP); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); +fapi_try_exit: + return fapi2::current_err; } /// @@ -642,25 +924,28 @@ void xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 4H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R17_MAP(0b00010); constexpr uint64_t DBIT_MAP(0b0001); // We're just like a 2R 2H 3DS 8Gbx4 so lets start there and modify - xlate_dimm_2R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + + // We're a 18 row DIMM, so ROW17 is valid. + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); - // Add in Row 17 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(R17_MAP); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); +fapi_try_exit: + return fapi2::current_err; } /// @@ -672,30 +957,32 @@ void xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 8H 3DS 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t M1_MAP(0b00100); constexpr uint64_t R15_MAP(0b00011); constexpr uint64_t DBIT_MAP(0b00010); // We're just like a 1R 8H 4Gbx4 so lets start there - xlate_dimm_1R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); // We need to setup our M1 bit - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID + i_offset); - io_xlate0.insertFromRight(M1_MAP); + FAPI_TRY( set_xlate_mrank(M1_MAP, i_offset, io_xlate0) ); - // Add in Row 15 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + i_offset); - io_xlate0.insertFromRight(R15_MAP); + // We're a 16 row DIMM, so ROW15 is valid. + FAPI_TRY( set_xlate_row(R15_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -707,25 +994,28 @@ void xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 8H 3DS 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP(0b00010); constexpr uint64_t DBIT_MAP(0b00001); // We're just like a 2R 8H 3DS 4Gbx4 DDR4 RDIMM - xlate_dimm_2R16T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R16T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // Add in Row 16 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(R16_MAP); + // We're a 17 row DIMM, so ROW16 is valid. + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -737,25 +1027,28 @@ void xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 8H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R17_MAP(0b00001); constexpr uint64_t DBIT_MAP(0b0000); // We're just like a 2R 8H 3DS 8Gbx4 DDR4 RDIMM - xlate_dimm_2R16T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R16T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // Add in Row 17 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(R17_MAP); + // We're a 18 row DIMM, so ROW17 is valid. + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } @@ -768,19 +1061,20 @@ void xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { bool l_all_slots_1R = all_slots_1R_helper(i_kind.iv_target); // Set the proper bit if there is a DIMM in this slot. If there wasn't, we wouldn't see // this DIMM in the vector, so this is always safe. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_VALID + i_offset); + FAPI_TRY(set_xlate_dimm_slot(i_offset, io_xlate0) ); // If we have all the slots filled in with 1R SDP DIMM, we build a very differnt mapping. if (l_all_slots_1R) @@ -790,8 +1084,7 @@ void xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, // Tell the MC which of the row bits are valid, and map the DIMM selector // We're a 16 row DIMM, so ROW15 is valid. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + i_offset); - io_xlate0.insertFromRight(R15_MAP); + FAPI_TRY( set_xlate_row(R15_MAP, i_offset, io_xlate0) ); // Drop down the column assignments. column_and_16bank_helper(io_xlate1, io_xlate2); @@ -800,64 +1093,65 @@ void xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, FAPI_INF("setting d-bit mapping (all 1R DIMM) for %s", mss::c_str(i_kind.iv_target)); io_xlate0.insertFromRight(DBIT_MAP); - return; + return fapi2::FAPI2_RC_SUCCESS; } // So if we're here we have only 1 1R DIMM installed. This translation is different. // Tell the MC which of the row bits are valid, and map the DIMM selector - // We're a 16 row DIMM, so ROW15 is valid. - - constexpr uint64_t COL4_MAP(0b01110); - constexpr uint64_t COL5_MAP(0b01101); - constexpr uint64_t COL6_MAP(0b01100); - constexpr uint64_t COL7_MAP(0b01011); - constexpr uint64_t COL8_MAP(0b01010); - constexpr uint64_t COL9_MAP(0b01001); - constexpr uint64_t BANK0_MAP(0b01111); - constexpr uint64_t BANK1_MAP(0b10000); - constexpr uint64_t BG0_MAP(0b10001); - constexpr uint64_t BG1_MAP(0b10010); - constexpr uint64_t R15_MAP(0b00111); - - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + i_offset); - io_xlate0.insertFromRight(R15_MAP); + { + constexpr uint64_t COL4_MAP(0b01110); + constexpr uint64_t COL5_MAP(0b01101); + constexpr uint64_t COL6_MAP(0b01100); + constexpr uint64_t COL7_MAP(0b01011); + constexpr uint64_t COL8_MAP(0b01010); + constexpr uint64_t COL9_MAP(0b01001); + constexpr uint64_t BANK0_MAP(0b01111); + constexpr uint64_t BANK1_MAP(0b10000); + constexpr uint64_t BG0_MAP(0b10001); + constexpr uint64_t BG1_MAP(0b10010); + constexpr uint64_t R15_MAP(0b00111); - // We don't just drop down the col and bank assignments, they're different. - io_xlate1.insertFromRight(COL4_MAP); + // We're a 16 row DIMM, so ROW15 is valid. + FAPI_TRY( set_xlate_row(R15_MAP, i_offset, io_xlate0) ); - io_xlate1.insertFromRight(COL5_MAP); + // We don't just drop down the col and bank assignments, they're different. + io_xlate1.insertFromRight(COL4_MAP); - io_xlate1.insertFromRight(COL6_MAP); + io_xlate1.insertFromRight(COL5_MAP); - io_xlate1.insertFromRight(COL7_MAP); + io_xlate1.insertFromRight(COL6_MAP); - io_xlate2.insertFromRight(COL8_MAP); + io_xlate1.insertFromRight(COL7_MAP); - io_xlate2.insertFromRight(COL9_MAP); + io_xlate2.insertFromRight(COL8_MAP); - io_xlate2.insertFromRight(BANK0_MAP); + io_xlate2.insertFromRight(COL9_MAP); - io_xlate2.insertFromRight(BANK1_MAP); + io_xlate2.insertFromRight(BANK0_MAP); - io_xlate2.insertFromRight(BG0_MAP); + io_xlate2.insertFromRight(BANK1_MAP); - io_xlate2.insertFromRight(BG1_MAP); + io_xlate2.insertFromRight(BG0_MAP); + io_xlate2.insertFromRight(BG1_MAP); + } // There's nothing to do for the D-bit. We're either not the largest DIMM, in which case the largest DIMM // will fix up our D-bit mapping, or we're the only DIMM in the port. If we're the only DIMM in the port, // there is no D-bit mapping for a 1 slot 1R DIMM. - return; + +fapi_try_exit: + return fapi2::current_err; } /// @@ -869,30 +1163,32 @@ void xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 8Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP_ALL_1R(0b00110); constexpr uint64_t R16_MAP_NOT_ALL_1R(0b00101); + const auto R16_MAP = all_slots_1R_helper(i_kind.iv_target) ? R16_MAP_ALL_1R : R16_MAP_NOT_ALL_1R; // We're more or less a 1R 4Gbx4 with an extra row. So lets setup like that and add our row in. - xlate_dimm_1R1T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R1T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); // If we have all the slots filled in with 1R SDP DIMM, we build a differnt mapping. - // Add the 17th row - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(all_slots_1R_helper(i_kind.iv_target) ? R16_MAP_ALL_1R : R16_MAP_NOT_ALL_1R); + // We're a 17 row DIMM, so ROW16 is valid. + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); // There's nothing to do for the D-bit. We're either not the largest DIMM, in which case the largest DIMM // will fix up our D-bit mapping, or we're the only DIMM in the port. If we're the only DIMM in the port, // there is no D-bit mapping for a 1 slot 1R DIMM. - return; + +fapi_try_exit: + return fapi2::current_err; } /// @@ -904,30 +1200,32 @@ void xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { - constexpr uint64_t R16_MAP_ALL_1R(0b00101); - constexpr uint64_t R16_MAP_NOT_ALL_1R(0b00100); + constexpr uint64_t R17_MAP_ALL_1R(0b00101); + constexpr uint64_t R17_MAP_NOT_ALL_1R(0b00100); + const auto R17_MAP = all_slots_1R_helper(i_kind.iv_target) ? R17_MAP_ALL_1R : R17_MAP_NOT_ALL_1R; // We're more or less a 1R 8Gbx4 with an extra row. So lets setup like that and add our row in. - xlate_dimm_1R1T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R1T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // If we have all the slots filled in with 1R SDP DIMM, we build a differnt mapping. - // Add the 18th row - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(all_slots_1R_helper(i_kind.iv_target) ? R16_MAP_ALL_1R : R16_MAP_NOT_ALL_1R); + // If we have all the slots filled in with 1R SDP DIMM, we build a different mapping. + // We're a 18 row DIMM, so ROW17 is valid. + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); // There's nothing to do for the D-bit. We're either not the largest DIMM, in which case the largest DIMM // will fix up our D-bit mapping, or we're the only DIMM in the port. If we're the only DIMM in the port, // there is no D-bit mapping for a 1 slot 1R DIMM. - return; + +fapi_try_exit: + return fapi2::current_err; } /// @@ -939,25 +1237,26 @@ void xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 2H 3DS 4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { - constexpr uint64_t CLEAR_MAP(0b00000); constexpr uint64_t S2_MAP(0b01111); // We're just like a 2R 4Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_2R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - io_xlate0.clearBit(MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID + i_offset); - io_xlate0.insertFromRight(CLEAR_MAP); + clear_xlate_mrank(i_offset, io_xlate0); - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_S2_VALID + i_offset); - io_xlate1.insertFromRight(S2_MAP); + FAPI_TRY( set_xlate_srank(S2_MAP, i_offset, io_xlate0, io_xlate1) ); + +fapi_try_exit: + return fapi2::current_err; } @@ -970,26 +1269,28 @@ void xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 2H 3DS 8Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP(0b00101); constexpr uint64_t DBIT_MAP(0b00100); // We're just like a 1R 2H 4Gbx4 so lets start there - xlate_dimm_1R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // Add in Row 16 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(R16_MAP); + // We're a 17 row DIMM, so ROW16 is valid. + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); +fapi_try_exit: + return fapi2::current_err; } /// @@ -1001,26 +1302,28 @@ void xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 2H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R17_MAP(0b00100); constexpr uint64_t DBIT_MAP(0b00011); // We're just like a 1R 2H 8Gbx4 so lets start there - xlate_dimm_1R2T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R2T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // Add in Row 17 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(R17_MAP); + // We're a 18 row DIMM, so ROW17 is valid. + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); +fapi_try_exit: + return fapi2::current_err; } /// @@ -1032,31 +1335,33 @@ void xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 4H 3DS 4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t S1_MAP(0b00110); constexpr uint64_t R15_MAP(0b00101); constexpr uint64_t DBIT_MAP(0b00100); // We're just like a 1R 2H 4Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_1R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); // What was row 15 is now a slave rank, and we have to add in row 15 and the d-bit - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID + i_offset); - io_xlate1.insertFromRight(S1_MAP); + FAPI_TRY( set_xlate_srank(S1_MAP, i_offset, io_xlate0, io_xlate1) ); - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + i_offset); - io_xlate0.insertFromRight(R15_MAP); + // We're a 16 row DIMM, so ROW15 is valid. + FAPI_TRY( set_xlate_row(R15_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); -} + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief Perform initializations of the MC translation @@ -1067,26 +1372,28 @@ void xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 4H 3DS 8Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP(0b00100); constexpr uint64_t DBIT_MAP(0b00011); // We're just like a 1R 4H 4Gbx4 so lets start there and modify - xlate_dimm_1R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // Add in Row 16 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(R16_MAP); + // We're a 17 row DIMM, so ROW16 is valid. + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); +fapi_try_exit: + return fapi2::current_err; } /// @@ -1098,25 +1405,28 @@ void xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 4H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R17_MAP(0b00011); constexpr uint64_t DBIT_MAP(0b00010); // We're just like a 1R 4H 8Gbx4 so lets start there and modify - xlate_dimm_1R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); - // Add in Row 17 - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(R17_MAP); + // We're a 18 row DIMM, so ROW17 is valid. + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -1128,29 +1438,30 @@ void xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 8H 3DS 4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t S0_MAP(0b00101); constexpr uint64_t R15_MAP(0b00100); constexpr uint64_t DBIT_MAP(0b00011); // We're just like a 1R 4H 4Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_1R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); - - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID + i_offset); - io_xlate1.insertFromRight(S0_MAP); + FAPI_TRY( xlate_dimm_1R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + FAPI_TRY( set_xlate_srank(S0_MAP, i_offset, io_xlate0, io_xlate1) ); // We're a 16 row DIMM, so ROW15 is valid. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID + i_offset); - io_xlate0.insertFromRight(R15_MAP); + FAPI_TRY( set_xlate_row(R15_MAP, i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); +fapi_try_exit: + return fapi2::current_err; } /// @@ -1162,25 +1473,28 @@ void xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 8H 3DS 8Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP(0b00011); constexpr uint64_t DBIT_MAP(0b00010); // We're just like a 1R 8H 4Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_1R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R8T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); // We're a 17 row DIMM, so ROW16 is valid. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(R16_MAP); + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -1192,25 +1506,28 @@ void xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 8H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R17_MAP(0b00010); constexpr uint64_t DBIT_MAP(0b00001); // We're just like a 1R 8H 8Gbx4 so lets start there and modify for the slave ranks. - xlate_dimm_1R8T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_1R8T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); // We're a 18 row DIMM, so ROW17 is valid. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(R17_MAP); + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); + + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); +fapi_try_exit: + return fapi2::current_err; } /// @@ -1222,28 +1539,31 @@ void xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 4R 4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R15_MAP(0b00101); constexpr uint64_t M0_MAP(0b00110); constexpr uint64_t DBIT_MAP(0b00100); // We're just like a 2R 4Gbx4 except we have a valid M0 and a different DIMM bit. - xlate_dimm_2R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_2R2T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); // Our R15 is still valid, but slide it over to make room for the M0 bit io_xlate0.insertFromRight(R15_MAP); - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_M0_VALID + i_offset); - io_xlate0.insertFromRight(M0_MAP); + FAPI_TRY( set_xlate_mrank(M0_MAP, i_offset, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; } /// @@ -1255,24 +1575,28 @@ void xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 4R 8Gbx4 DDR4 RDIMM -/// -void xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R16_MAP(0b00100); constexpr uint64_t DBIT_MAP(0b00011); // We're just like a 4R 4Gbx4 except we have an extra row - xlate_dimm_4R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_4R4T4Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + + // We're a 17 row DIMM, so ROW16 is valid. + FAPI_TRY( set_xlate_row(R16_MAP, i_offset, io_xlate0) ); - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID + i_offset); - io_xlate0.insertFromRight(R16_MAP); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); +fapi_try_exit: + return fapi2::current_err; } /// @@ -1284,40 +1608,44 @@ void xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 4R 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_4R4T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ) +fapi2::ReturnCode xlate_dimm_4R4T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ) { constexpr uint64_t R17_MAP(0b00011); constexpr uint64_t DBIT_MAP(0b00010); // We're just like a 4R 8Gbx4 except we have an extra row - xlate_dimm_4R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( xlate_dimm_4R4T8Gbx4(i_kind, i_offset, i_largest, io_xlate0, io_xlate1, io_xlate2) ); + + // We're a 18 row DIMM, so ROW17 is valid. + FAPI_TRY( set_xlate_row(R17_MAP, i_offset, io_xlate0) ); - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID + i_offset); - io_xlate0.insertFromRight(R17_MAP); + FAPI_TRY( d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0) ); - d_bit_helper(i_kind.iv_target, i_largest, i_offset, DBIT_MAP, io_xlate0); +fapi_try_exit: + return fapi2::current_err; } /// /// @brief Helper to setup the translation map - useful for testing -/// @param[in] i_dimm_kinds std::vector of DIMM kind's representing the DIMM (Not const as we sort the vector) +/// @param[in,out] io_dimm_kinds std::vector of DIMM kind's representing the DIMM (Not const as we sort the vector) /// @param[out] fapi2::buffer io_xlate00 - xlt register 0's value /// @param[out] fapi2::buffer io_xlate1 - xlt register 1's value /// @param[out] fapi2::buffer io_xlate2 - xlt register 2's value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode setup_xlate_map_helper( std::vector& i_dimm_kinds, +fapi2::ReturnCode setup_xlate_map_helper( std::vector& io_dimm_kinds, fapi2::buffer& io_xlate0, fapi2::buffer& io_xlate1, fapi2::buffer& io_xlate2 ) { - if (i_dimm_kinds.size() < 1) + if (io_dimm_kinds.size() < 1) { FAPI_ERR("seeing an empty vector in the setup_xlate_map_helper"); fapi2::Assert(false); @@ -1328,32 +1656,32 @@ fapi2::ReturnCode setup_xlate_map_helper( std::vector& i_dimm_kinds, // However, we need to set that DIMM's D bit in the location of the largest DIMM's D-bit map (I know that's // hard to grok - set the D bit in the smallest DIMM but in the location mapped for the largest.) So we // keep track of the largest DIMM so when we set it up, we make sure to set the D-bit in the other. - std::sort(i_dimm_kinds.begin(), i_dimm_kinds.end(), [](const dimm::kind & a, const dimm::kind & b) -> bool + std::sort(io_dimm_kinds.begin(), io_dimm_kinds.end(), [](const dimm::kind & a, const dimm::kind & b) -> bool { return a.iv_size > b.iv_size; }); - FAPI_INF("DIMM with the largest size on this port is %s %dMR (%d total ranks) %dgbx%d (%dG)", - mss::c_str(i_dimm_kinds[0].iv_target), - i_dimm_kinds[0].iv_master_ranks, - i_dimm_kinds[0].iv_total_ranks, - i_dimm_kinds[0].iv_dram_density, - i_dimm_kinds[0].iv_dram_width, - i_dimm_kinds[0].iv_size); + FAPI_INF("DIMM with the largest size on this port is %s %dMR (%d total ranks) %dGbx%d (%dGB)", + mss::c_str(io_dimm_kinds[0].iv_target), + io_dimm_kinds[0].iv_master_ranks, + io_dimm_kinds[0].iv_total_ranks, + io_dimm_kinds[0].iv_dram_density, + io_dimm_kinds[0].iv_dram_width, + io_dimm_kinds[0].iv_size); - const auto l_d_bit_target = i_dimm_kinds[0].iv_target; + const auto l_d_bit_target = io_dimm_kinds[0].iv_target; // Get the functional DIMM on this port. - for (const auto& k : i_dimm_kinds) + for (const auto& k : io_dimm_kinds) { // Our slot (0, 1) is the same as our general index. const uint64_t l_slot = mss::index(k.iv_target); - // Our slot offset tells us which 16 bit section in the xlt register to use for this DIMM + // Our slot offset tells us which 16 bit secption in the xlt register to use for this DIMM // We'll either use the left most bits (slot 0) or move 16 bits to the right for slot 1. const uint64_t l_slot_offset = l_slot * 16; - FAPI_INF("address translation for DIMM %s %dMR (%d total ranks) %dgbx%d (%dG) in slot %d", + FAPI_INF("address translation for DIMM %s %dMR (%d total ranks) %dGbx%d (%dGB) in slot %d", mss::c_str(k.iv_target), k.iv_master_ranks, k.iv_total_ranks, @@ -1364,7 +1692,7 @@ fapi2::ReturnCode setup_xlate_map_helper( std::vector& i_dimm_kinds, // Set the proper bit if there is a DIMM in this slot. If there wasn't, we wouldn't see // this DIMM in the vector, so this is always safe. - io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_VALID + l_slot_offset); + FAPI_TRY(set_xlate_dimm_slot(l_slot_offset, io_xlate0) ); // Find the proper set function based on this DIMM kind. const auto l_setup = std::find_if( xlate_map.begin(), xlate_map.end(), [k](const xlate_setup & x) -> bool @@ -1384,7 +1712,7 @@ fapi2::ReturnCode setup_xlate_map_helper( std::vector& i_dimm_kinds, set_DIMM_TYPE(k.iv_dimm_type). set_ROWS(k.iv_rows). set_SIZE(k.iv_size), - "no address translation funtion for DIMM %s %dMR (%d total ranks) %dgbx%d (%dG) in slot %d", + "no address translation funtion for DIMM %s %dMR (%d total ranks) %dGbx%d (%dGB) in slot %d", mss::c_str(k.iv_target), k.iv_master_ranks, k.iv_total_ranks, @@ -1395,16 +1723,19 @@ fapi2::ReturnCode setup_xlate_map_helper( std::vector& i_dimm_kinds, // If we did find it ... // If we're the smallest DIMM in the port and we have more than one DIMM, we set our D-bit. - if( (l_d_bit_target != k.iv_target) && (i_dimm_kinds.size() > 1) ) + if( (l_d_bit_target != k.iv_target) && (io_dimm_kinds.size() > 1) ) { FAPI_INF("noting d-bit of 1 for %s", mss::c_str(k.iv_target)); - io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_D_VALUE + l_slot_offset); + FAPI_TRY( io_xlate0.setBit(MCS_PORT13_MCP0XLT0_SLOT0_D_VALUE + l_slot_offset) ); + + FAPI_DBG("Set d-bit. MCP0XLT0: 0x%016lx, MCP0XLT1: 0x%016lx, MCP0XLT2: 0x%016lx", + uint64_t(io_xlate0), uint64_t(io_xlate1), uint64_t(io_xlate2) ); } // Call the translation function to fill in the blanks. - // The conditional argument tells the setup function whether this setup sould set the D bit, as we're + // The conditional argument tells the setup function whether this setup should set the D bit, as we're // the largest DIMM on the port. - l_setup->iv_func(k, l_slot_offset, (k.iv_target == l_d_bit_target), io_xlate0, io_xlate1, io_xlate2); + FAPI_TRY( l_setup->iv_func(k, l_slot_offset, (k.iv_target == l_d_bit_target), io_xlate0, io_xlate1, io_xlate2) ); } FAPI_INF("cramming 0x%016lx in for MCP0XLT0", io_xlate0); @@ -1428,7 +1759,7 @@ fapi2::ReturnCode setup_xlate_map(const fapi2::Target& i_target fapi2::buffer l_xlate1; fapi2::buffer l_xlate2; - const auto l_dimms = i_target.getChildren(); + const auto l_dimms = mss::find_targets(i_target); // We need to keep around specifications of both DIMM as we set the D bit based on the sizes of the DIMM std::vector l_dimm_kinds = dimm::kind::vector(l_dimms); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H index e59d86d77..ab85bb6a6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H @@ -52,6 +52,386 @@ namespace mss namespace mc { +enum rows +{ + ROW15, + ROW16, + ROW17, +}; + +enum xlate_ranks +{ + // Master ranks + M0, + M1, + + // Slave ranks + S0, + S1, + S2, +}; + +/// +/// @class rowTraits +/// @brief a collection of traits associated with the row xlate registers +/// @tparam T rows enumeration to represent xlate row bits +/// +template< rows T > +class rowTraits; + +/// +/// @class rowTraits +/// @brief a collection of traits associated with the row xlate registers +/// +template< > +class rowTraits +{ + public: + static constexpr uint64_t ROW = 15; + static constexpr uint64_t MAX_MAP_VALUE = 0b00111; + + enum + { + SLOT0_ROW_VALID = MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID, + ROW_BIT_MAP = MCS_PORT02_MCP0XLT0_R15_BIT_MAP, + ROW_BIT_MAP_LEN = MCS_PORT02_MCP0XLT0_R15_BIT_MAP_LEN, + }; +}; + +/// +/// @class rowTraits +/// @brief a collection of traits associated with the row xlate registers +/// +template< > +class rowTraits +{ + public: + static constexpr uint64_t ROW = 16; + static constexpr uint64_t MAX_MAP_VALUE = 0b00111; + + enum + { + SLOT0_ROW_VALID = MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID, + ROW_BIT_MAP = MCS_PORT02_MCP0XLT0_R16_BIT_MAP, + ROW_BIT_MAP_LEN = MCS_PORT02_MCP0XLT0_R16_BIT_MAP_LEN, + }; +}; + +/// +/// @class rowTraits +/// @brief a collection of traits associated with the row xlate registers +/// +template< > +class rowTraits +{ + public: + static constexpr uint64_t ROW = 17; + static constexpr uint64_t MAX_MAP_VALUE = 0b00111; + ; + enum + { + SLOT0_ROW_VALID = MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID, + ROW_BIT_MAP = MCS_PORT02_MCP0XLT0_R17_BIT_MAP, + ROW_BIT_MAP_LEN = MCS_PORT02_MCP0XLT0_R17_BIT_MAP_LEN, + }; +}; + +/// +/// @brief Sets row bits on the xlate register +/// @tparam T row enumerations to represent xlate master row bits +/// @tparam TT traits type defaults to rowTraits +/// @param[in] i_map value to set master rank bit map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< rows T, typename TT = rowTraits > +inline fapi2::ReturnCode set_xlate_row(const uint64_t i_map, + const uint64_t i_offset, + fapi2::buffer& io_xlate0) +{ + if( i_map > TT::MAX_MAP_VALUE) + { + FAPI_ERR("Received a map value (%d) greater than the max value allowed by MCP0XLT0_R%d_BIT_MAP (%d)", + i_map, TT::ROW, TT::MAX_MAP_VALUE); + + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + FAPI_TRY( io_xlate0.setBit( TT::SLOT0_ROW_VALID + i_offset ) ); + io_xlate0.insertFromRight(i_map); + + FAPI_DBG( "Set MCP0XLT0_SLOT%d_ROW%d_VALID at bit %d. " + "Set bits for MCP0XLT0_R%d_BIT_MAP with 0x%lx (start: %d, len: %d). " + "MCP0XLT0: 0x%016lx.", + (i_offset == 0 ? 0 : 1), TT::ROW, TT::SLOT0_ROW_VALID + i_offset, TT::ROW, + i_map, TT::ROW_BIT_MAP, TT::ROW_BIT_MAP_LEN, + uint64_t(io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @class mrankTraits +/// @brief a collection of traits associated with the master rank xlate registers +/// @tparam T rank enumerations to represent xlate master rank bits +/// +template < xlate_ranks T> +class mrankTraits; + +/// +/// @class mrankTraits +/// @brief a collection of traits associated with the master rank xlate registers +/// +template< > +class mrankTraits +{ + public: + static constexpr uint64_t RANK = 0; + static constexpr uint64_t CLEAR_MAP = 0b00000; + static constexpr uint64_t MAX_MAP_VALUE = 0b111; + enum + { + SLOT0_VALID = MCS_PORT13_MCP0XLT0_SLOT0_M0_VALID, + BIT_MAP = MCS_PORT02_MCP0XLT0_M0_BIT_MAP, + BIT_MAP_LEN = MCS_PORT02_MCP0XLT0_M0_BIT_MAP_LEN, + }; +}; + +/// +/// @class mrankTraits +/// @brief a collection of traits associated with the master rank xlate registers +/// +template< > +class mrankTraits +{ + public: + static constexpr uint64_t RANK = 1; + static constexpr uint64_t CLEAR_MAP = 0b00000; + static constexpr uint64_t MAX_MAP_VALUE = 0b10010; + + enum + { + SLOT0_VALID = MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID, + BIT_MAP = MCS_PORT02_MCP0XLT0_M1_BIT_MAP, + BIT_MAP_LEN = MCS_PORT02_MCP0XLT0_M1_BIT_MAP_LEN, + }; +}; + +/// +/// @brief Sets master rank bits on the xlate register +/// @tparam T rank enumerations to represent xlate master rank bits +/// @tparam TT traits type defaults to mrankTraits +/// @param[in] i_map value to set master rank bit map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< xlate_ranks T, typename TT = mrankTraits > +inline fapi2::ReturnCode set_xlate_mrank(const uint64_t i_map, + const uint64_t i_offset, + fapi2::buffer& io_xlate0) +{ + if( i_map > TT::MAX_MAP_VALUE) + { + FAPI_ERR("Received a map value (%d) greater than the max value allowed by MCP0XLT0_M%d_BIT_MAP (%d)", + i_map, TT::RANK, TT::MAX_MAP_VALUE); + + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + FAPI_TRY( io_xlate0.setBit(TT::SLOT0_VALID + i_offset) ); + io_xlate0.insertFromRight(i_map); + + FAPI_DBG("Set MCP0XLT0_SLOT%d_M%d_VALID at bit %d. Set MCP0XLT0_M%d_BIT_MAP with 0x%lx (start: %d, len: %d). " + "MCP0XLT0: 0x%016lx.", + (i_offset == 0 ? 0 : 1), TT::RANK, TT::SLOT0_VALID + i_offset, + TT::RANK, uint64_t(i_map), TT::BIT_MAP, TT::BIT_MAP_LEN, + uint64_t(io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Clears master rank bits on the xlate register +/// @tparam T rank enumerations to represent xlate master rank bits +/// @tparam TT traits type defaults to mrankTraits +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< xlate_ranks T, typename TT = mrankTraits > +inline fapi2::ReturnCode clear_xlate_mrank(const uint64_t i_offset, + fapi2::buffer& io_xlate0) +{ + FAPI_TRY( io_xlate0.clearBit(TT::SLOT0_VALID + i_offset) ); + io_xlate0.insertFromRight(TT::CLEAR_MAP); + + FAPI_DBG("Set MCP0XLT0_SLOT%d_M%d_VALID at bit %d. Set MCP0XLT0_M%d_BIT_MAP with 0x%lx (start: %d, len: %d). " + "MCP0XLT0: 0x%016lx.", + (i_offset == 0 ? 0 : 1), TT::RANK, TT::SLOT0_VALID + i_offset, + TT::RANK, TT::CLEAR_MAP, TT::BIT_MAP, TT::BIT_MAP_LEN, + uint64_t(io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @class srankTraits +/// @brief a collection of traits associated with the slave rank xlate registers +/// @tparam T rank enumerations to represent xlate slave rank bits +/// +template < xlate_ranks T> +class srankTraits; + +/// +/// @class srankTraits +/// @brief a collection of traits associated with the slave rank xlate registers +/// for slave rank 0 +/// +template< > +class srankTraits +{ + public: + static constexpr uint64_t RANK = 0; + static constexpr uint64_t CLEAR_MAP = 0b00000; + static constexpr uint64_t MAX_MAP_VALUE = 0b10010; + + enum + { + SLOT0_VALID = MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID, + BIT_MAP = MCS_PORT02_MCP0XLT1_S0_BIT_MAP, + BIT_MAP_LEN = MCS_PORT02_MCP0XLT1_S0_BIT_MAP_LEN, + }; +}; + +/// +/// @class srankTraits +/// @brief a collection of traits associated with the slave rank xlate registers +/// for slave rank 1 +/// +template< > +class srankTraits +{ + public: + static constexpr uint64_t RANK = 1; + static constexpr uint64_t CLEAR_MAP = 0b00000; + static constexpr uint64_t MAX_MAP_VALUE = 0b10010; + + enum + { + SLOT0_VALID = MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID, + BIT_MAP = MCS_PORT02_MCP0XLT1_S1_BIT_MAP, + BIT_MAP_LEN = MCS_PORT02_MCP0XLT1_S1_BIT_MAP_LEN, + }; +}; + +/// +/// @class srankTraits +/// @brief a collection of traits associated with the slave rank xlate registers +/// for slave rank 2 +/// +template< > +class srankTraits +{ + public: + static constexpr uint64_t RANK = 2; + static constexpr uint64_t CLEAR_MAP = 0b00000; + static constexpr uint64_t MAX_MAP_VALUE = 0b10010; + + enum + { + SLOT0_VALID = MCS_PORT13_MCP0XLT0_SLOT0_S2_VALID, + BIT_MAP = MCS_PORT02_MCP0XLT1_S2_BIT_MAP, + BIT_MAP_LEN = MCS_PORT02_MCP0XLT1_S2_BIT_MAP_LEN, + }; +}; + +/// +/// @brief Sets slave rank bits on the xlate register +/// @tparam T rank enumerations to represent xlate slave rank bits +/// @tparam TT traits type defaults to srankTraits +/// @param[in] i_map value to set slave rank bit map +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< xlate_ranks T, typename TT = srankTraits > +inline fapi2::ReturnCode set_xlate_srank(const uint64_t i_map, + const uint64_t i_offset, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1) +{ + if( i_map > TT::MAX_MAP_VALUE) + { + FAPI_ERR("Received a map value (%d) greater than the max value allowed by MCP0XLT0_S%d_BIT_MAP (%d)", + i_map, TT::RANK, TT::MAX_MAP_VALUE); + + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + FAPI_TRY( io_xlate0.setBit(TT::SLOT0_VALID + i_offset) ); + io_xlate1.insertFromRight(i_map); + + FAPI_DBG("Set MCP0XLT0_SLOT%d_S%d_VALID at bit %d. Set MCP0XLT0_S%d_BIT_MAP with 0x%lx (start: %d, len: %d). " + "MCP0XLT0: 0x%016lx, MCP0XLT1: 0x%016lx.", + (i_offset == 0 ? 0 : 1), TT::RANK, TT::SLOT0_VALID + i_offset, + TT::RANK, uint64_t(i_map), TT::BIT_MAP, TT::BIT_MAP_LEN, + uint64_t(io_xlate0), uint64_t(io_xlate1) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Clears slave rank bits on the xlate register +/// @tparam T rank enumerations to represent xlate slave rank bits +/// @tparam TT traits type defaults to srankTraits +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @param[in,out] io_xlate1 a buffer representing the xlate register to modify +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< xlate_ranks T, typename TT = srankTraits > +inline fapi2::ReturnCode clear_xlate_srank(const uint64_t i_offset, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1) +{ + FAPI_TRY( io_xlate0.clearBit(TT::SLOT0_VALID + i_offset) ); + io_xlate1.insertFromRight(TT::CLEAR_MAP); + + FAPI_DBG("Set MCP0XLT0_SLOT%d_S%d_VALID at bit %d. Set MCP0XLT0_S%d_BIT_MAP with 0x%lx (start: %d, len: %d). " + "MCP0XLT0: 0x%016lx, MCP0XLT1: 0x%016lx.", + (i_offset == 0 ? 0 : 1), TT::RANK, TT::SLOT0_VALID + i_offset, + TT::RANK, TT::CLEAR_MAP, TT::BIT_MAP, TT::BIT_MAP_LEN, + uint64_t(io_xlate0), uint64_t(io_xlate1) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Set DIMM slot bits +/// @param[in] i_offset the offset; whether the DIMM is in slot 0 or slot 1 +/// @param[in,out] io_xlate0 a buffer representing the xlate register to modify +/// @return FAPI2_RC_SUCCESS iff okay +/// +inline fapi2::ReturnCode set_xlate_dimm_slot(const uint64_t i_offset, + fapi2::buffer& io_xlate0) +{ + FAPI_TRY( io_xlate0.setBit(MCS_PORT02_MCP0XLT0_SLOT0_VALID + i_offset) ); + + FAPI_DBG("Set MCP0XLT0_SLOT%d_VALID at bit %d. MCP0XLT0: 0x%016lx.", + (i_offset == 0 ? 0 : 1), MCS_PORT02_MCP0XLT0_SLOT0_VALID + i_offset, uint64_t(io_xlate0) ); + +fapi_try_exit: + return fapi2::current_err; +} + /// /// @brief A small class to represent the setup of a translation register based on DIMM characteristics /// @@ -63,8 +443,8 @@ struct xlate_setup /// @param[in] i_func a function pointer to a function which does the configuring /// xlate_setup( const dimm::kind i_kind, - void (*i_func)( const dimm::kind&, const uint64_t, const bool, - fapi2::buffer&, fapi2::buffer&, fapi2::buffer& ) ): + fapi2::ReturnCode (*i_func)( const dimm::kind&, const uint64_t, const bool, + fapi2::buffer&, fapi2::buffer&, fapi2::buffer& ) ): iv_kind(i_kind), iv_func(i_func) { @@ -74,11 +454,10 @@ struct xlate_setup dimm::kind iv_kind; // The function to call to setup the translation registers to setup for our DIMM kind. - void (*iv_func)( const dimm::kind&, const uint64_t, const bool, - fapi2::buffer&, fapi2::buffer&, fapi2::buffer& ); + fapi2::ReturnCode (*iv_func)( const dimm::kind&, const uint64_t, const bool, + fapi2::buffer&, fapi2::buffer&, fapi2::buffer& ); }; - /// /// @brief Perform initializations of the MC translation /// @param[in] i_kind the DIMM to map @@ -88,13 +467,14 @@ struct xlate_setup /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -105,13 +485,14 @@ void xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -122,13 +503,14 @@ void xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -139,13 +521,14 @@ void xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 2H 3DS 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -156,13 +539,14 @@ void xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 2H 3DS 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -173,13 +557,14 @@ void xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 2H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -190,13 +575,14 @@ void xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 4H 3DS 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -207,13 +593,14 @@ void xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 4H 3DS 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -224,13 +611,14 @@ void xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 4H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -241,13 +629,14 @@ void xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 8H 3DS 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -258,13 +647,14 @@ void xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 8H 3DS 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation /// @param[in] i_kind the DIMM to map @@ -274,13 +664,14 @@ void xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 2R 8H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -291,13 +682,14 @@ void xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation /// @param[in] i_kind the DIMM to map @@ -307,13 +699,14 @@ void xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -324,13 +717,14 @@ void xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -341,13 +735,14 @@ void xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 2H 3DS 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -358,13 +753,14 @@ void xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 2H 3DS 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -375,13 +771,14 @@ void xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 2H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -392,13 +789,14 @@ void xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 4H 3DS 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -409,13 +807,14 @@ void xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 4H 3DS 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -426,13 +825,14 @@ void xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 4H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation /// @param[in] i_kind the DIMM to map @@ -442,13 +842,14 @@ void xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 8H 3DS 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation /// @param[in] i_kind the DIMM to map @@ -458,13 +859,14 @@ void xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 8H 3DS 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -475,13 +877,14 @@ void xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 8H 3DS 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -492,13 +895,14 @@ void xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 4R 4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation /// @param[in] i_kind the DIMM to map @@ -508,13 +912,14 @@ void xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 4R 8Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation /// @param[in] i_kind the DIMM to map @@ -524,13 +929,14 @@ void xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 4R 16Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_4R4T16Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_4R4T16Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Helper to setup the translation map - useful for testing /// @param[in] i_dimm_kinds std::vector of DIMM kind's representing the DIMM (Not const as we sort the vector) @@ -553,13 +959,14 @@ fapi2::ReturnCode setup_xlate_map_helper( std::vector& i_dimm_kinds, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R4Gbx4 DDR4 RDIMM +/// @return FAPI2_RC_SUCCESS iff okay /// -void xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); /// /// @brief Perform initializations of the MC translation @@ -570,13 +977,14 @@ void xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, /// @param[in,out] io_xlate1 a buffer representing the xlate register to modify /// @param[in,out] io_xlate2 a buffer representing the xlate register to modify /// @note Called for 1R 2 total ranks 4Gbx4 DDR4 RDIMM -/// -void xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, - const uint64_t i_offset, - const bool i_largest, - fapi2::buffer& io_xlate0, - fapi2::buffer& io_xlate1, - fapi2::buffer& io_xlate2 ); +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, + const uint64_t i_offset, + const bool i_largest, + fapi2::buffer& io_xlate0, + fapi2::buffer& io_xlate1, + fapi2::buffer& io_xlate2 ); } // ns mc -- cgit v1.2.1