From 5889ecc567fe8ce43e3527268551422435dbb283 Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Tue, 29 Mar 2016 09:37:44 -0500 Subject: Change PHY PC, RC and DP16 register blocks to functional API Change-Id: I37fe3b5204defdced954976aabffdfdc1dde91e1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23015 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: JACOB L. HARVEY Reviewed-by: Louis Stermole Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23016 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/memory/lib/phy/ddr_phy.C | 39 +- .../chips/p9/procedures/hwp/memory/lib/phy/dp16.C | 63 +- .../chips/p9/procedures/hwp/memory/lib/phy/dp16.H | 223 ++++--- .../p9/procedures/hwp/memory/lib/phy/phy_cntrl.H | 204 +++--- .../p9/procedures/hwp/memory/lib/phy/read_cntrl.H | 684 +++++++++++---------- .../p9/procedures/hwp/memory/lib/phy/write_cntrl.H | 23 +- .../procedures/hwp/memory/p9_mss_ddr_phy_reset.C | 2 +- .../hwp/memory/p9_mss_draminit_training.C | 2 +- 8 files changed, 625 insertions(+), 615 deletions(-) (limited to 'src/import') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 00410c57b..a33840220 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -49,8 +49,6 @@ using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCS; using fapi2::TARGET_TYPE_DIMM; -using fapi2::FAPI2_RC_SUCCESS; - namespace mss { @@ -90,6 +88,7 @@ fapi2::ReturnCode toggle_zctl( const fapi2::Target& i_target fapi2::buffer l_data; const auto l_ports = i_target.getChildren(); + // // 4. Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset and enable the internal impedance controller. // (SCOM Addr: 0x8000C0140301143F, 0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F) @@ -148,8 +147,9 @@ fapi2::ReturnCode change_force_mclk_low (const fapi2::Target // Might as well do this for all the ports while we're here. for (const auto& p : i_target.getChildren()) { - FAPI_TRY(mss::getScom( p, MCA_MBA_FARB5Q, l_data)); + FAPI_TRY( mss::getScom(p, MCA_MBA_FARB5Q, l_data) ); + // TK: use writeBit? if (i_state == mss::HIGH) { l_data.setBit(); @@ -421,10 +421,9 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// template<> -fapi2::ReturnCode rank_pair_primary_to_dimm( - const fapi2::Target& i_target, - const uint64_t i_rp, - fapi2::Target& o_dimm) +fapi2::ReturnCode rank_pair_primary_to_dimm( const fapi2::Target& i_target, + const uint64_t i_rp, + fapi2::Target& o_dimm) { fapi2::buffer l_data; fapi2::buffer l_rank; @@ -477,8 +476,6 @@ fapi2::ReturnCode rank_pair_primary_to_dimm( o_dimm = l_dimms[l_rank_on_dimm]; - return FAPI2_RC_SUCCESS; - fapi_try_exit: return fapi2::current_err; } @@ -502,8 +499,6 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target l_fir_data; fapi2::buffer l_err_data; - mss::pc l_pc; - fapi2::Target l_failed_dimm; FAPI_TRY( mss::apb::read_fir_err1(i_target, l_fir_data) ); @@ -512,7 +507,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target(l_errors); l_err_data.extractToRight(l_rank_pairs); @@ -553,7 +548,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target& i_target std::vector l_pairs; // Setup the DP16 IO TX, DLL/VREG. They use freq which is an MCBIST attribute - FAPI_TRY( mss::dp16().setup_io_tx_config0(i_target) ); - FAPI_TRY( mss::dp16().setup_dll_vreg_config1(i_target) ); + FAPI_TRY( mss::dp16::reset_io_tx_config0(i_target) ); + FAPI_TRY( mss::dp16::reset_dll_vreg_config1(i_target) ); for (const auto& p : i_target.getChildren()) { - mss::dp16 l_dp16; - // The following registers must be configured to the correct operating environment: // Undocumented, noted by Bialas @@ -804,14 +797,14 @@ fapi2::ReturnCode phy_scominit(const fapi2::Target& i_target // Section 5.2.4.2 DP16 Data Bit Enable 1 on page 285 // Section 5.2.4.3 DP16 Data Bit Disable 0 on page 288 // Section 5.2.4.4 DP16 Data Bit Disable 1 on page 289 - FAPI_TRY( l_dp16.write_data_bit_enable(p) ); - FAPI_TRY( l_dp16.set_bad_bits(p) ); + FAPI_TRY( mss::dp16::reset_data_bit_enable(p) ); + FAPI_TRY( mss::dp16::reset_bad_bits(p) ); FAPI_TRY( mss::get_rank_pairs(p, l_pairs) ); // Section 5.2.4.8 DP16 Write Clock Enable & Clock Selection on page 301 - FAPI_TRY( l_dp16.write_clock_enable(p, l_pairs) ); - FAPI_TRY( l_dp16.read_clock_enable(p, l_pairs) ); + FAPI_TRY( mss::dp16::reset_write_clock_enable(p, l_pairs) ); + FAPI_TRY( mss::dp16::reset_read_clock_enable(p, l_pairs) ); // Write Control reset FAPI_TRY( mss::wc::reset(p) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index bf30d0e8a..c3687e030 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -36,6 +36,7 @@ #include #include +#include #include #include @@ -48,6 +49,9 @@ using fapi2::TARGET_TYPE_SYSTEM; namespace mss { +namespace dp16 +{ + typedef std::pair< uint64_t, uint64_t > register_data_pair; typedef std::vector< register_data_pair > register_data_vector; @@ -140,12 +144,11 @@ static std::vector< register_data_vector > rdclk_enable_spare_x4 = }; /// -/// @brief Write the data bit enable registers +/// @brief Reset the data bit enable registers /// @param[in] i_target a port target /// @return FAPI2_RC_SUCCES iff ok /// -template<> -fapi2::ReturnCode dp16::write_data_bit_enable( const fapi2::Target& i_target ) +fapi2::ReturnCode reset_data_bit_enable( const fapi2::Target& i_target ) { // Determine if we're running with spares or not. Once we know that, we can find the right vector to iterate over. // Note: Is this ATTR_EFF_DIMM_SPARE? Because that's per DIMM, but this is a port-level statement, right? BRS @@ -158,7 +161,7 @@ fapi2::ReturnCode dp16::write_data_bit_enable( const fapi2::Tar FAPI_DBG("reg/data vector %d", l_reg_data.size()); - for (auto rdp : l_reg_data) + for (const auto& rdp : l_reg_data) { // This is probably important enough to be seen all the time, not just debug FAPI_INF( "Setting up DATA_BIT_ENABLE 0x%llx (0x%llx) %s", rdp.first, rdp.second, mss::c_str(i_target) ); @@ -170,22 +173,21 @@ fapi_try_exit: } /// -/// @brief Write the clock enable registers +/// @brief Reset the read clock enable registers /// @param[in] i_target /// @param[in] l_rank_pairs /// @return FAPI2_RC_SUCCES iff ok /// -template<> -fapi2::ReturnCode dp16::read_clock_enable( const fapi2::Target& i_target, +fapi2::ReturnCode reset_read_clock_enable( const fapi2::Target& i_target, const std::vector< uint64_t >& l_rank_pairs ) { // Just slam something in here for now - we know the 'RIT DIMM' is x4, lets assume no cross-coupling for now bool l_using_spares = false; auto l_reg_data = l_using_spares ? rdclk_enable_spare_x4[0] : rdclk_enable_no_spare_x4[0]; - for (auto rp : l_rank_pairs) + for (const auto& rp : l_rank_pairs) { - for (auto rdp : l_reg_data) + for (const auto& rdp : l_reg_data) { // Grab the register and add the rank pair in fapi2::buffer l_address(rdp.first); @@ -204,22 +206,21 @@ fapi_try_exit: } /// -/// @brief Write the read clock enable registers +/// @brief Resets the write clock enable registers /// @param[in] i_target /// @param[in] l_rank_pairs /// @return FAPI2_RC_SUCCESs iff ok /// -template<> -fapi2::ReturnCode dp16::write_clock_enable( const fapi2::Target& i_target, +fapi2::ReturnCode reset_write_clock_enable( const fapi2::Target& i_target, const std::vector< uint64_t >& l_rank_pairs ) { // Just slam something in here for now - we know the 'RIT DIMM' is x4, lets assume no cross-coupling for now bool l_using_spares = false; auto l_reg_data = l_using_spares ? wrclk_enable_spare_x4[0] : wrclk_enable_no_spare_x4[0]; - for (auto rp : l_rank_pairs) + for (const auto& rp : l_rank_pairs) { - for (auto rdp : l_reg_data) + for (const auto& rdp : l_reg_data) { // Grab the register and add the rank pair in fapi2::buffer l_address(rdp.first); @@ -243,9 +244,8 @@ fapi_try_exit: /// @param[in] l_rank_pairs vector of rank pairs /// @return FAPI2_RC_SUCCES iff ok /// -template<> -fapi2::ReturnCode dp16::reset_delay_values( const fapi2::Target& i_target, - const std::vector< uint64_t >& l_rank_pairs ) +fapi2::ReturnCode reset_delay_values( const fapi2::Target& i_target, + const std::vector< uint64_t >& l_rank_pairs ) { std::vector l_addrs( { @@ -260,13 +260,13 @@ fapi2::ReturnCode dp16::reset_delay_values( const fapi2::Target // Reset the write level values FAPI_INF( "Resetting write level values %s", mss::c_str(i_target) ); - FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) ); - l_data.setBit(); - FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) ); + FAPI_TRY( mss::wc::read_config2(i_target, l_data) ); + mss::wc::set_reset_wr_delay_wl(l_data); + FAPI_TRY( mss::wc::write_config2(i_target, l_data) ); - for (auto rp : l_rank_pairs) + for (const auto& rp : l_rank_pairs) { - for (auto a : l_addrs) + for (const auto& a : l_addrs) { // Add the rank pair into the register to get the actual address fapi2::buffer l_address(a); @@ -286,9 +286,7 @@ fapi_try_exit: /// @param[in] i_target a MCBIST target /// @return FAPI2_RC_SUCCESs iff ok /// -template<> -template<> -fapi2::ReturnCode dp16::setup_sysclk( const fapi2::Target& i_target ) +fapi2::ReturnCode reset_sysclk( const fapi2::Target& i_target ) { std::vector< std::pair > l_addrs( { @@ -310,11 +308,11 @@ fapi2::ReturnCode dp16::setup_sysclk( const fapi2::Target(); } - for (auto p : i_target.getChildren()) + for (const auto& p : i_target.getChildren()) { FAPI_DBG("set dp16_sysclk for %s", mss::c_str(p)); - for (auto a : l_addrs) + for (const auto& a : l_addrs) { FAPI_TRY( mss::putScom(p, a.first, l_data) ); FAPI_TRY( mss::putScom(p, a.second, l_data) ); @@ -331,9 +329,7 @@ fapi_try_exit: /// @param[in] i_target a MCBIST target /// @return FAPI2_RC_SUCCESS iff ok /// -template<> -template<> -fapi2::ReturnCode dp16::setup_io_tx_config0( const fapi2::Target& i_target ) +fapi2::ReturnCode reset_io_tx_config0( const fapi2::Target& i_target ) { static const std::vector l_addrs( { @@ -369,9 +365,7 @@ fapi_try_exit: /// @param[in] i_target a MCBIST target /// @return FAPI2_RC_SUCCESs iff ok /// -template<> -template<> -fapi2::ReturnCode dp16::setup_dll_vreg_config1( const fapi2::Target& i_target ) +fapi2::ReturnCode reset_dll_vreg_config1( const fapi2::Target& i_target ) { static const std::vector l_addrs( { @@ -400,4 +394,5 @@ fapi_try_exit: } -} +} // close namespace dp16 +} // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index 389dc51c8..bed4e6e77 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -99,99 +99,107 @@ class dp16Traits { }; +namespace dp16 +{ + + /// -/// @class mss::dp16 -/// @brief PHY DP16 Block class -/// @tparam T fapi2 Target Type -/// @tparam TT traits type defaults to dp16Traits +/// @brief Configure the DP16 sysclk +/// @tparam T the fapi2 target type +/// @tparam TT the target traits +/// @param[in] i_target a target +/// @return FAPI2_RC_SUCCESs iff ok /// template< fapi2::TargetType T, typename TT = dp16Traits > -class dp16 -{ - public: - - /// - /// @brief Configure the DP16 sysclk - /// @tparam K the fapi2 target type - /// @param[in] i_target a target - /// @return FAPI2_RC_SUCCESs iff ok - /// - template< fapi2::TargetType K > - fapi2::ReturnCode setup_sysclk( const fapi2::Target& i_target ); - - /// - /// @brief Reset the training delay configureation - /// @tparam T the type of the port - /// @param[in] i_target the port target - /// @param[in] l_rank_pairs vector of rank pairs - /// @return FAPI2_RC_SUCCES iff ok - /// - fapi2::ReturnCode reset_delay_values( const fapi2::Target& i_target, - const std::vector< uint64_t >& l_rank_pairs ); - - /// - /// @brief Write the read clock enable registers - /// @tparam T the type of the port - /// @param[in] i_target a port target - /// @param[in] l_rank_pairs vector of rank pairs - /// @return FAPI2_RC_SUCCES iff ok - /// - fapi2::ReturnCode read_clock_enable( const fapi2::Target& i_target, - const std::vector< uint64_t >& l_rank_pairs ); - - /// - /// @brief Write the clock enable registers - /// @tparam T the type of the port - /// @param[in] i_target a port target - /// @param[in] l_rank_pairs vector of rank pairs - /// @return FAPI2_RC_SUCCES iff ok - /// - fapi2::ReturnCode write_clock_enable( const fapi2::Target& i_target, - const std::vector< uint64_t >& l_rank_pairs ); - - /// - /// @brief Write the data bit enable registers - /// @tparam T the type of the port - /// @param[in] i_target a port target - /// @return FAPI2_RC_SUCCESs iff ok - /// - fapi2::ReturnCode write_data_bit_enable( const fapi2::Target& i_target ); - - - /// - /// @brief Setup the bad-bits masks for a port - /// @tparam T the fapi2::TargetType - /// @param[in] i_target the target (MCA or MBA?) - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - inline fapi2::ReturnCode set_bad_bits(const fapi2::Target& i_target); - - /// - /// @brief Configure the DP16 io_tx config0 registers - /// @param[in] i_target a fapi2 target - /// @return FAPI2_RC_SUCCESs iff ok - /// - template< fapi2::TargetType K> - fapi2::ReturnCode setup_io_tx_config0( const fapi2::Target& i_target ); - - /// - /// @brief Configure ADR DLL/VREG Config 1 - /// @param[in] i_target a fapi2 target - /// @return FAPI2_RC_SUCCESs iff ok - /// - template - fapi2::ReturnCode setup_dll_vreg_config1( const fapi2::Target& i_target ); -}; +fapi2::ReturnCode reset_sysclk( const fapi2::Target& i_target ); + +/// +/// @brief Reset the training delay configureation +/// @tparam T the type of the port +/// @tparam TT the target traits +/// @param[in] i_target the port target +/// @param[in] l_rank_pairs vector of rank pairs +/// @return FAPI2_RC_SUCCES iff ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +fapi2::ReturnCode reset_delay_values( const fapi2::Target& i_target, + const std::vector< uint64_t >& l_rank_pairs ); + +/// +/// @brief Reset the read clock enable registers +/// @tparam T the type of the port +/// @tparam TT the target traits +/// @param[in] i_target a port target +/// @param[in] l_rank_pairs vector of rank pairs +/// @return FAPI2_RC_SUCCES iff ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +fapi2::ReturnCode reset_read_clock_enable( const fapi2::Target& i_target, + const std::vector< uint64_t >& l_rank_pairs ); + +/// +/// @brief Resets the write clock enable registers +/// @tparam T the type of the port +/// @tparam TT the target traits +/// @param[in] i_target a port target +/// @param[in] l_rank_pairs vector of rank pairs +/// @return FAPI2_RC_SUCCES iff ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +fapi2::ReturnCode reset_write_clock_enable( const fapi2::Target& i_target, + const std::vector< uint64_t >& l_rank_pairs ); + +/// +/// @brief Reset the data bit enable registers +/// @tparam T the type of the port +/// @tparam TT the target traits +/// @param[in] i_target a port target +/// @return FAPI2_RC_SUCCESs iff ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +fapi2::ReturnCode reset_data_bit_enable( const fapi2::Target& i_target ); + + +/// +/// @brief Reset the bad-bits masks for a port +/// @tparam T the fapi2::TargetType +/// @tparam TT the target traits +/// @param[in] i_target the target (MCA or MBA?) +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +inline fapi2::ReturnCode reset_bad_bits(const fapi2::Target& i_target); + +/// +/// @brief Configure the DP16 io_tx config0 registers +/// @tparam T the fapi2::TargetType +/// @tparam TT the target traits +/// @param[in] i_target a fapi2 target +/// @return FAPI2_RC_SUCCESs iff ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +fapi2::ReturnCode reset_io_tx_config0( const fapi2::Target& i_target ); + +/// +/// @brief Configure ADR DLL/VREG Config 1 +/// @tparam T the fapi2::TargetType +/// @tparam TT the target traits +/// @param[in] i_target a fapi2 target +/// @return FAPI2_RC_SUCCESs iff ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +fapi2::ReturnCode reset_dll_vreg_config1( const fapi2::Target& i_target ); + +/// +/// Specializations +/// /// /// @brief Configure the DP16 sysclk /// @param[in] i_target a MCBIST target /// @return FAPI2_RC_SUCCESs iff ok /// -template<> -template<> -fapi2::ReturnCode dp16::setup_sysclk( - const fapi2::Target& i_target ); +fapi2::ReturnCode reset_sysclk( const fapi2::Target& i_target ); /// /// @brief Reset the training delay configureation @@ -199,51 +207,41 @@ fapi2::ReturnCode dp16::setup_sysclk( /// @param[in] l_rank_pairs vector of rank pairs /// @return FAPI2_RC_SUCCES iff ok /// -template<> -fapi2::ReturnCode dp16::reset_delay_values( - const fapi2::Target& i_target, - const std::vector< uint64_t >& l_rank_pairs ); +fapi2::ReturnCode reset_delay_values( const fapi2::Target& i_target, + const std::vector< uint64_t >& l_rank_pairs ); /// -/// @brief Write the clock enable registers +/// @brief Reset the read clock enable registers /// @param[in] i_target a port target /// @param[in] l_rank_pairs vector of rank pairs /// @return FAPI2_RC_SUCCES iff ok /// -template<> -fapi2::ReturnCode dp16::read_clock_enable( - const fapi2::Target& i_target, - const std::vector< uint64_t >& l_rank_pairs ); +fapi2::ReturnCode reset_read_clock_enable( const fapi2::Target& i_target, + const std::vector< uint64_t >& l_rank_pairs ); /// -/// @brief Write the clock enable registers +/// @brief Reset the write clock enable registers /// @param[in] i_target a port target /// @param[in] l_rank_pairs vector of rank pairs /// @return FAPI2_RC_SUCCES iff ok /// -template<> -fapi2::ReturnCode dp16::write_clock_enable( - const fapi2::Target& i_target, - const std::vector< uint64_t >& l_rank_pairs ); +fapi2::ReturnCode reset_write_clock_enable( const fapi2::Target& i_target, + const std::vector< uint64_t >& l_rank_pairs ); /// -/// @brief Write the data bit enable registers +/// @brief Reset the data bit enable registers /// @param[in] i_target a port target /// @return FAPI2_RC_SUCCESs iff ok /// -template<> -fapi2::ReturnCode dp16::write_data_bit_enable( - const fapi2::Target& i_target ); +fapi2::ReturnCode reset_data_bit_enable( const fapi2::Target& i_target ); /// -/// @brief Setup the bad-bits masks for a port +/// @brief Reset the bad-bits masks for a port /// @tparam T the fapi2::TargetType /// @param[in] i_target the target (MCA or MBA?) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template<> -inline fapi2::ReturnCode dp16::set_bad_bits( - const fapi2::Target& i_target) +inline fapi2::ReturnCode reset_bad_bits( const fapi2::Target& i_target) { // Note: We need to do this ... BRS return fapi2::FAPI2_RC_SUCCESS; @@ -254,21 +252,16 @@ inline fapi2::ReturnCode dp16::set_bad_bits( /// @param[in] i_target a MCBIST target /// @return FAPI2_RC_SUCCESs iff ok /// -template<> -template<> -fapi2::ReturnCode dp16::setup_io_tx_config0( - const fapi2::Target& i_target ); +fapi2::ReturnCode reset_io_tx_config0( const fapi2::Target& i_target ); /// /// @brief Configure ADR DLL/VREG Config 1 /// @param[in] i_target a MCBIST target /// @return FAPI2_RC_SUCCESs iff ok /// -template<> -template<> -fapi2::ReturnCode dp16::setup_dll_vreg_config1( - const fapi2::Target& i_target ); +fapi2::ReturnCode reset_dll_vreg_config1( const fapi2::Target& i_target ); -} +} // close namespace dp16 +} // close namespace mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H index e6bfafc7f..e4c9f4da2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/phy_cntrl.H @@ -88,116 +88,116 @@ class pcTraits }; +namespace pc +{ + + /// -/// @class mss::pc -/// @brief Phy Control Class -/// @tparam T fapi2 Target Type -/// @tparam TT traits type defaults to pcTraits +/// @brief read PC_ERROR_STATUS0 +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok /// template< fapi2::TargetType T, typename TT = pcTraits > -class pc +inline fapi2::ReturnCode read_error_status0( const fapi2::Target& i_target, fapi2::buffer& o_data ) { - public: + FAPI_TRY( mss::getScom(i_target, TT::PC_ERROR_STATUS0_REG, o_data) ); + FAPI_DBG("pc_error_status0: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} - /// - /// @brief read PC_ERROR_STATUS0 - /// @param[in] i_target the fapi2 target of the port - /// @param[out] o_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - inline fapi2::ReturnCode read_error_status0( const fapi2::Target& i_target, fapi2::buffer& o_data ) - { - FAPI_TRY( mss::getScom(i_target, TT::PC_ERROR_STATUS0_REG, o_data) ); - FAPI_DBG("pc_error_status0: 0x%016llx", o_data); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Write PC_ERROR_STATUS0 - /// @param[in] i_target the fapi2 target of the port - /// @param[in] i_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - inline fapi2::ReturnCode write_error_status0( const fapi2::Target& i_target, - const fapi2::buffer& i_data ) - { - FAPI_DBG("pc_error_status0: 0x%016llx", i_data); - FAPI_TRY( mss::putScom(i_target, TT::PC_ERROR_STATUS0_REG, i_data) ); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief reset pc_error_status0 - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - inline fapi2::ReturnCode reset_error_status0( const fapi2::Target& i_target ) - { - FAPI_TRY( write_error_status0(i_target, 0) ); - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief read PC_INIT_CAL_ERROR - /// @param[in] i_target the fapi2 target of the port - /// @param[out] o_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - inline fapi2::ReturnCode read_init_cal_error( const fapi2::Target& i_target, fapi2::buffer& o_data ) - { - FAPI_TRY( mss::getScom(i_target, TT::PC_INIT_CAL_ERROR_REG, o_data) ); - FAPI_DBG("pc_init_cal_error: 0x%016llx", o_data); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Write PC_INIT_CAL_ERROR - /// @param[in] i_target the fapi2 target of the port - /// @param[in] i_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - inline fapi2::ReturnCode write_init_cal_error( const fapi2::Target& i_target, - const fapi2::buffer& i_data ) - { - FAPI_DBG("pc_init_cal_error: 0x%016llx", i_data); - FAPI_TRY( mss::putScom(i_target, TT::PC_INIT_CAL_ERROR_REG, i_data) ); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief reset pc_init_cal_error - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - inline fapi2::ReturnCode reset_init_cal_error( const fapi2::Target& i_target ) - { - FAPI_TRY( write_init_cal_error(i_target, 0) ); - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief reset rc - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok - /// - inline fapi2::ReturnCode reset( const fapi2::Target& i_target ) - { - FAPI_TRY( reset_error_status0(i_target) ); +/// +/// @brief Write PC_ERROR_STATUS0 +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = pcTraits > +inline fapi2::ReturnCode write_error_status0( const fapi2::Target& i_target, + const fapi2::buffer& i_data ) +{ + FAPI_DBG("pc_error_status0: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::PC_ERROR_STATUS0_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief reset pc_error_status0 +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = pcTraits > +inline fapi2::ReturnCode reset_error_status0( const fapi2::Target& i_target ) +{ + FAPI_TRY( write_error_status0(i_target, 0) ); - fapi_try_exit: - return fapi2::current_err; - } +fapi_try_exit: + return fapi2::current_err; +} -}; +/// +/// @brief read PC_INIT_CAL_ERROR +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = pcTraits > +inline fapi2::ReturnCode read_init_cal_error( const fapi2::Target& i_target, fapi2::buffer& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::PC_INIT_CAL_ERROR_REG, o_data) ); + FAPI_DBG("pc_init_cal_error: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write PC_INIT_CAL_ERROR +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = pcTraits > +inline fapi2::ReturnCode write_init_cal_error( const fapi2::Target& i_target, + const fapi2::buffer& i_data ) +{ + FAPI_DBG("pc_init_cal_error: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::PC_INIT_CAL_ERROR_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief reset pc_init_cal_error +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = pcTraits > +inline fapi2::ReturnCode reset_init_cal_error( const fapi2::Target& i_target ) +{ + FAPI_TRY( write_init_cal_error(i_target, 0) ); + +fapi_try_exit: + return fapi2::current_err; +} +/// +/// @brief reset rc +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = pcTraits > +inline fapi2::ReturnCode reset( const fapi2::Target& i_target ) +{ + FAPI_TRY( reset_error_status0(i_target) ); + FAPI_TRY( reset_init_cal_error(i_target) ); + +fapi_try_exit: + return fapi2::current_err; } +} // close namespace pc +} // close namespace mss + #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H index 61bb61001..ced06fa23 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/read_cntrl.H @@ -120,367 +120,375 @@ class rcTraits }; +namespace rc +{ + /// -/// @class mss::rc -/// @brief Read Control reset config 0 -/// @tparam T fapi2 Target Type - derived -/// @tparam TT traits type defaults to rcTraits +/// @brief Read RC_VREF_CONFIG0 +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = rcTraits > -class rc_class +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode read_vref_config0( const fapi2::Target& i_target, fapi2::buffer& o_data ) { - public: + FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG0_REG, o_data) ); + FAPI_DBG("rc_vref_config0: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} - /// - /// @brief Read RC_VREF_CONFIG0 - /// @param[in] i_target the fapi2 target of the port - /// @param[out] o_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode read_vref_config0( const fapi2::Target& i_target, fapi2::buffer& o_data ) - { - FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG0_REG, o_data) ); - FAPI_DBG("rc_vref_config0: 0x%016llx", o_data); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Write RC_VREF_CONFIG0 - /// @param[in] i_target the fapi2 target of the port - /// @param[in] i_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode write_vref_config0( const fapi2::Target& i_target, - const fapi2::buffer& i_data ) - { - FAPI_DBG("rc_vref_config0: 0x%016llx", i_data); - FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG0_REG, i_data) ); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Read RC_VREF_CONFIG1 - /// @param[in] i_target the fapi2 target of the port - /// @param[out] o_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode read_vref_config1( const fapi2::Target& i_target, fapi2::buffer& o_data ) - { - FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG1_REG, o_data) ); - FAPI_DBG("rc_vref_config1: 0x%016llx", o_data); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Write RC_VREF_CONFIG1 - /// @param[in] i_target the fapi2 target of the port - /// @param[in] i_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode write_vref_config1( const fapi2::Target& i_target, - const fapi2::buffer& i_data ) - { - FAPI_DBG("rc_vref_config1: 0x%016llx", i_data); - FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG1_REG, i_data) ); - fapi_try_exit: - return fapi2::current_err; - } - - - /// - /// @brief Read RC_CONFIG0 - /// @param[in] i_target the fapi2 target of the port - /// @param[out] o_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode read_config0( const fapi2::Target& i_target, fapi2::buffer& o_data ) - { - FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG0_REG, o_data) ); - FAPI_DBG("rc_config0: 0x%016llx", o_data); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Write RC_CONFIG0 - /// @param[in] i_target the fapi2 target of the port - /// @param[in] i_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode write_config0( const fapi2::Target& i_target, const fapi2::buffer& i_data ) - { - FAPI_DBG("rc_config0: 0x%016llx", i_data); - FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG0_REG, i_data) ); - fapi_try_exit: - return fapi2::current_err; - } - - - /// - /// @brief Read RC_CONFIG1 - /// @param[in] i_target the fapi2 target of the port - /// @param[out] o_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode read_config1( const fapi2::Target& i_target, fapi2::buffer& o_data ) - { - FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG1_REG, o_data) ); - FAPI_DBG("rc_config1: 0x%016llx", o_data); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Write RC_CONFIG1 - /// @param[in] i_target the fapi2 target of the port - /// @param[in] i_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode write_config1( const fapi2::Target& i_target, const fapi2::buffer& i_data ) - { - FAPI_DBG("rc_config1: 0x%016llx", i_data); - FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG1_REG, i_data) ); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Read RC_CONFIG2 - /// @param[in] i_target the fapi2 target of the port - /// @param[out] o_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode read_config2( const fapi2::Target& i_target, fapi2::buffer& o_data ) - { - FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG2_REG, o_data) ); - FAPI_DBG("rc_config2: 0x%016llx", o_data); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Write RC_CONFIG2 - /// @param[in] i_target the fapi2 target of the port - /// @param[in] i_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode write_config2( const fapi2::Target& i_target, const fapi2::buffer& i_data ) - { - FAPI_DBG("rc_config2: 0x%016llx", i_data); - FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG2_REG, i_data) ); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Read RC_CONFIG3 - /// @param[in] i_target the fapi2 target of the port - /// @param[out] o_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode read_config3( const fapi2::Target& i_target, fapi2::buffer& o_data ) - { - FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG3_REG, o_data) ); - FAPI_DBG("rc_config3: 0x%016llx", o_data); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Write RC_CONFIG3 - /// @param[in] i_target the fapi2 target of the port - /// @param[in] i_data the value of the register - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode write_config3( const fapi2::Target& i_target, const fapi2::buffer& i_data ) - { - FAPI_DBG("rc_config3: 0x%016llx", i_data); - FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG3_REG, i_data) ); - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief reset rc_config0 - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode reset_config0( const fapi2::Target& i_target ) - { - fapi2::buffer l_data; - uint8_t l_gpo = 0; +/// +/// @brief Write RC_VREF_CONFIG0 +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode write_vref_config0( const fapi2::Target& i_target, + const fapi2::buffer& i_data ) +{ + FAPI_DBG("rc_vref_config0: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG0_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} - FAPI_TRY( mss::vpd_gpo(i_target, l_gpo) ); +/// +/// @brief Read RC_VREF_CONFIG1 +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode read_vref_config1( const fapi2::Target& i_target, fapi2::buffer& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::RC_VREF_CONFIG1_REG, o_data) ); + FAPI_DBG("rc_vref_config1: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} - // 48:51, (ATTR_VPD_GPO[0]), any; # GLOBAL_PHY_OFFSET (GPO), based on attribute now - l_data.insertFromRight(l_gpo); +/// +/// @brief Write RC_VREF_CONFIG1 +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode write_vref_config1( const fapi2::Target& i_target, + const fapi2::buffer& i_data ) +{ + FAPI_DBG("rc_vref_config1: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::RC_VREF_CONFIG1_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} - l_data.setBit(); - FAPI_TRY( write_config0(i_target, l_data) ); +/// +/// @brief Read RC_CONFIG0 +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode read_config0( const fapi2::Target& i_target, fapi2::buffer& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG0_REG, o_data) ); + FAPI_DBG("rc_config0: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} - fapi_try_exit: - return fapi2::current_err; - } +/// +/// @brief Write RC_CONFIG0 +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode write_config0( const fapi2::Target& i_target, const fapi2::buffer& i_data ) +{ + FAPI_DBG("rc_config0: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG0_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} - /// - /// @brief reset rc_config1 - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode reset_config1( const fapi2::Target& i_target ) - { - fapi2::buffer l_data; - // Centaur was all 0's ... - FAPI_TRY( write_config1(i_target, l_data) ); +/// +/// @brief Read RC_CONFIG1 +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode read_config1( const fapi2::Target& i_target, fapi2::buffer& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG1_REG, o_data) ); + FAPI_DBG("rc_config1: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} - fapi_try_exit: - return fapi2::current_err; - } +/// +/// @brief Write RC_CONFIG1 +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode write_config1( const fapi2::Target& i_target, const fapi2::buffer& i_data ) +{ + FAPI_DBG("rc_config1: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG1_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} - /// - /// @brief reset rc_config2 - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode reset_config2( const fapi2::Target& i_target ) - { - fapi2::buffer l_data; - uint8_t is_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), is_sim) ); - - // Bogus Centaur SIM number from init file - use 8 per Bialas 2/16 - // ---48:52, 0b00000, (def_is_sim); # CONSEQ_PASS sim value--- - // 48:52, 0b01000, (def_is_bl8); # CONSEQ_PASS 8 from SWyatt - // 48:52, 0b01111, any; # CONSEQ_PASS 16 min for BL4, or OTF - if (is_sim) - { - l_data.insertFromRight(0b01000); - } - else - { - uint8_t l_bl = 0; - - FAPI_TRY( mss::eff_dram_burst_length(i_target, l_bl) ); - l_data.insertFromRight( - l_bl == fapi2::ENUM_ATTR_EFF_DRAM_BL_BL8 ? 0b01000 : 0b01111); - } - - // 57:58, 0b11, any; # BURST_WINDOW, compare all 8 beats (AS recommended) - l_data.insertFromRight(0b11); - - FAPI_TRY( write_config2(i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief reset rc_config3 - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode reset_config3( const fapi2::Target& i_target ) - { - fapi2::buffer l_data; - uint8_t is_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), is_sim) ); - - // 51:54, 0b1010, (def_is_sim); # COARSE_CAL_STEP_SIZE» # old=4=5/128 (5/18) - // 51:54, 0b0000, any; # COARSE_CAL_STEP_SIZE = 1/128 - l_data.insertFromRight(is_sim ? 0b1010 : 0b0000); - - FAPI_TRY( write_config3(i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief reset rc_vref_config0 - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode reset_vref_config0( const fapi2::Target& i_target ) - { - fapi2::buffer l_data; - uint16_t l_guess_time = 0; - - // This 16 bit integer denotes the number of memory clock cycles to wait for the analog - // D/A converter to settle to a value. The digital value in the D/A converter can - // change every 500 KHz, so the frequency of dphy_gckn divided by the number in - // this register must be less than 500 KHz. Due to changing state machine states - // happening during this period, it is recommended to ensure the value used slightly - // exceeds the 500 KHz threshold. - // For example, a 1333 MHz clock must have value be slight more than 1333 MHz / - // 500 KHz = 2,666, rounded up to a final value of 2700. - // - // So this means we just add a smidge to MSS_FREQ, right? Round up to the nearest '00 - // and jump 100 if we're divisible by 100 (e.g., 2400. This should yield 2500.) - uint64_t l_freq; - FAPI_TRY( mss::freq(i_target.template getParent(), l_freq) ); - - l_guess_time = (l_freq + 100) / 100 * 100; - FAPI_INF("VREF guess wait time: %u (freq: %lu)", l_guess_time, l_freq); - - l_data.insertFromRight((l_freq + 100) / 100 * 100); - - FAPI_TRY( write_vref_config0(i_target, l_data) ); - - fapi_try_exit: - return fapi2::current_err; - } - - - /// - /// @brief reset rc_vref_config1 - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode reset_vref_config1( const fapi2::Target& i_target ) - { - fapi2::buffer l_data; +/// +/// @brief Read RC_CONFIG2 +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode read_config2( const fapi2::Target& i_target, fapi2::buffer& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG2_REG, o_data) ); + FAPI_DBG("rc_config2: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} - // TK: WAG at CMD_PRECEDE_TIME - l_data.insertFromRight(0 + 4 + 2); - l_data.insertFromRight(0); // TK: +/// +/// @brief Write RC_CONFIG2 +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode write_config2( const fapi2::Target& i_target, const fapi2::buffer& i_data ) +{ + FAPI_DBG("rc_config2: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG2_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} - // Note: when initial cal is setup, this register will change to accomodate the - // initial cal read centering and read vref centering cal steps. +/// +/// @brief Read RC_CONFIG3 +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode read_config3( const fapi2::Target& i_target, fapi2::buffer& o_data ) +{ + FAPI_TRY( mss::getScom(i_target, TT::RC_CONFIG3_REG, o_data) ); + FAPI_DBG("rc_config3: 0x%016llx", o_data); +fapi_try_exit: + return fapi2::current_err; +} - FAPI_TRY( write_vref_config1(i_target, l_data) ); +/// +/// @brief Write RC_CONFIG3 +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode write_config3( const fapi2::Target& i_target, const fapi2::buffer& i_data ) +{ + FAPI_DBG("rc_config3: 0x%016llx", i_data); + FAPI_TRY( mss::putScom(i_target, TT::RC_CONFIG3_REG, i_data) ); +fapi_try_exit: + return fapi2::current_err; +} - fapi_try_exit: - return fapi2::current_err; - } +/// +/// @brief reset rc_config0 +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode reset_config0( const fapi2::Target& i_target ) +{ + fapi2::buffer l_data; + uint8_t l_gpo = 0; - /// - /// @brief reset rc - /// @param[in] i_target fapi2 target of the port - /// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok - /// - static inline fapi2::ReturnCode reset( const fapi2::Target& i_target ) - { - FAPI_TRY( reset_config0(i_target) ); - FAPI_TRY( reset_config1(i_target) ); - FAPI_TRY( reset_config2(i_target) ); - FAPI_TRY( reset_config3(i_target) ); + FAPI_TRY( mss::vpd_gpo(i_target, l_gpo) ); - FAPI_TRY( reset_vref_config0(i_target) ); - FAPI_TRY( reset_vref_config1(i_target) ); + // 48:51, (ATTR_VPD_GPO[0]), any; # GLOBAL_PHY_OFFSET (GPO), based on attribute now + l_data.insertFromRight(l_gpo); - fapi_try_exit: - return fapi2::current_err; - } + l_data.setBit(); -}; + FAPI_TRY( write_config0(i_target, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief reset rc_config1 +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode reset_config1( const fapi2::Target& i_target ) +{ + fapi2::buffer l_data; + + // Centaur was all 0's ... + FAPI_TRY( write_config1(i_target, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief reset rc_config2 +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode reset_config2( const fapi2::Target& i_target ) +{ + fapi2::buffer l_data; + uint8_t is_sim = 0; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), is_sim) ); + + // Bogus Centaur SIM number from init file - use 8 per Bialas 2/16 + // ---48:52, 0b00000, (def_is_sim); # CONSEQ_PASS sim value--- + // 48:52, 0b01000, (def_is_bl8); # CONSEQ_PASS 8 from SWyatt + // 48:52, 0b01111, any; # CONSEQ_PASS 16 min for BL4, or OTF + if (is_sim) + { + l_data.insertFromRight(0b01000); + } + else + { + uint8_t l_bl = 0; + + FAPI_TRY( mss::eff_dram_burst_length(i_target, l_bl) ); + l_data.insertFromRight( + l_bl == fapi2::ENUM_ATTR_EFF_DRAM_BL_BL8 ? 0b01000 : 0b01111); + } + + // 57:58, 0b11, any; # BURST_WINDOW, compare all 8 beats (AS recommended) + l_data.insertFromRight(0b11); + + FAPI_TRY( write_config2(i_target, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} -using rc = rc_class; +/// +/// @brief reset rc_config3 +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode reset_config3( const fapi2::Target& i_target ) +{ + fapi2::buffer l_data; + uint8_t is_sim = 0; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), is_sim) ); + + // 51:54, 0b1010, (def_is_sim); # COARSE_CAL_STEP_SIZE» # old=4=5/128 (5/18) + // 51:54, 0b0000, any; # COARSE_CAL_STEP_SIZE = 1/128 + l_data.insertFromRight(is_sim ? 0b1010 : 0b0000); + + FAPI_TRY( write_config3(i_target, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief reset rc_vref_config0 +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode reset_vref_config0( const fapi2::Target& i_target ) +{ + fapi2::buffer l_data; + uint16_t l_guess_time = 0; + + // This 16 bit integer denotes the number of memory clock cycles to wait for the analog + // D/A converter to settle to a value. The digital value in the D/A converter can + // change every 500 KHz, so the frequency of dphy_gckn divided by the number in + // this register must be less than 500 KHz. Due to changing state machine states + // happening during this period, it is recommended to ensure the value used slightly + // exceeds the 500 KHz threshold. + // For example, a 1333 MHz clock must have value be slight more than 1333 MHz / + // 500 KHz = 2,666, rounded up to a final value of 2700. + // + // So this means we just add a smidge to MSS_FREQ, right? Round up to the nearest '00 + // and jump 100 if we're divisible by 100 (e.g., 2400. This should yield 2500.) + uint64_t l_freq; + FAPI_TRY( mss::freq(i_target.template getParent(), l_freq) ); + + l_guess_time = (l_freq + 100) / 100 * 100; + FAPI_INF("VREF guess wait time: %u (freq: %lu)", l_guess_time, l_freq); + + l_data.insertFromRight((l_freq + 100) / 100 * 100); + + FAPI_TRY( write_vref_config0(i_target, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief reset rc_vref_config1 +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode reset_vref_config1( const fapi2::Target& i_target ) +{ + fapi2::buffer l_data; + + // TK: WAG at CMD_PRECEDE_TIME + l_data.insertFromRight(0 + 4 + 2); + l_data.insertFromRight(0); // TK: + + // Note: when initial cal is setup, this register will change to accomodate the + // initial cal read centering and read vref centering cal steps. + + FAPI_TRY( write_vref_config1(i_target, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} +/// +/// @brief reset rc +/// @param[in] i_target fapi2 target of the port +/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = rcTraits > +inline fapi2::ReturnCode reset( const fapi2::Target& i_target ) +{ + FAPI_TRY( reset_config0(i_target) ); + FAPI_TRY( reset_config1(i_target) ); + FAPI_TRY( reset_config2(i_target) ); + FAPI_TRY( reset_config3(i_target) ); + + FAPI_TRY( reset_vref_config0(i_target) ); + FAPI_TRY( reset_vref_config1(i_target) ); + +fapi_try_exit: + return fapi2::current_err; } +} // close namespace rc +} // close namespace mss + #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H index 450790550..fbe64addc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H @@ -32,6 +32,8 @@ #include #include +#include +#include namespace mss { @@ -153,7 +155,6 @@ fapi_try_exit: return fapi2::current_err; } - /// /// @brief Read WC_CONFIG1 /// @tparam T fapi2 Target Type - derived @@ -417,6 +418,26 @@ fapi_try_exit: } +/// +/// @brief Set EN_RESET_WR_DELAY_WL +/// @param[in] io_data buffer to set +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits > +inline void set_reset_wr_delay_wl( fapi2::buffer& io_data ) +{ + io_data.setBit(); +} + +/// +/// @brief Get EN_RESET_WR_DELAY_WL +/// @param[in] io_data buffer to get value from +/// @return right-aligned uint64_t containing the contents of the field +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits > +inline uint64_t get_reset_wr_delay_wl( fapi2::buffer& io_data ) +{ + return io_data.getBit() ? 1 : 0; +} /// /// @brief reset wc_rtt_wr_swap_enable diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index 9186f9616..4c3dd6ebc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -62,7 +62,7 @@ extern "C" // // 1. Drive all control signals to the PHY to their inactive state, idle state, or inactive value. - FAPI_TRY( mss::dp16().setup_sysclk(i_target) ); + FAPI_TRY( mss::dp16::reset_sysclk(i_target) ); // (Note: The chip should already be in this state.) FAPI_DBG("All control signals to the PHYs should already be set to their inactive state, idle state, or inactive values"); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index f1b9c940f..d1bbaaeac 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -174,7 +174,7 @@ extern "C" // don't reset if we're running special training - assumes there's a checkpoint which has valid state. if ((l_reset_disable == fapi2::ENUM_ATTR_MSS_DRAMINIT_RESET_DISABLE_ENABLE) && (i_special_training == 0)) { - FAPI_TRY( mss::dp16().reset_delay_values(p, l_pairs) ); + FAPI_TRY( mss::dp16::reset_delay_values(p, l_pairs) ); } FAPI_DBG("generating calibration CCS instructions: %d rank-pairs", l_pairs.size()); -- cgit v1.2.1