From 39854a32f080c70d3aeeaadc5e947d9c2bd7704b Mon Sep 17 00:00:00 2001 From: Jenny Huynh Date: Mon, 19 Aug 2019 23:16:25 -0400 Subject: Add slbv, slbe extraction to p9_ram_core procedure Change-Id: I6efe5d4f8fbb9f893a2371acd108d9d1d3002ecd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82496 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Matt K Light Reviewed-by: Thi N Tran Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82504 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R Geddes --- src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C | 14 +++++++++++++- src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H | 6 ++++-- 2 files changed, 17 insertions(+), 3 deletions(-) (limited to 'src/import') diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C index 24d789f02..87e1d5b70 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,6 +49,8 @@ const uint32_t RAM_REG_MSR = 2001; const uint32_t RAM_REG_CR = 2002; const uint32_t RAM_REG_FPSCR = 2003; const uint32_t RAM_REG_VSCR = 2004; +const uint32_t RAM_REG_SLBE = 2005; +const uint32_t RAM_REG_SLBV = 2006; // opcode for ramming const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPRD = 0x7C1543A6; @@ -602,6 +604,16 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, opcodes[8] = {&l_backup_vr0_dw0, OPCODE_MFSPR_FROM_SPRD_TO_GPR0 + (1 << 21), NULL}; opcodes[9] = {NULL, OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32, NULL}; } + else if(i_reg_num == RAM_REG_SLBE) + { + opcodes[0] = {NULL, OPCODE_SLBMFEE, NULL}; + opcodes[1] = {NULL, OPCODE_MTSPR_FROM_GPR0_TO_SPRD, &o_buffer[0]}; + } + else if(i_reg_num == RAM_REG_SLBV) + { + opcodes[0] = {NULL, OPCODE_SLBMFEV, NULL}; + opcodes[1] = {NULL, OPCODE_MTSPR_FROM_GPR0_TO_SPRD, &o_buffer[0]}; + } else { //1.create mfspr opcode, ram into thread diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H index 6bf4ac961..abfc2effe 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -234,7 +234,9 @@ typedef std::map::iterator SPR_MAP_IT; _op_(MSR ,2001, ECP.SD.T_MSR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(CR ,2002, N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ _op_(FPSCR ,2003, N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ - _op_(VSCR ,2004, N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32) + _op_(VSCR ,2004, N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(SLBE ,2005, N/A ,FLAG_READ_ONLY ,SPR_PER_PT ,64)\ + _op_(SLBV ,2006, N/A ,FLAG_READ_ONLY ,SPR_PER_PT ,64) #define DO_SPR_MAP(in_name, in_number, in_spy_name, in_flag, in_share_type, in_bit_length)\ SPRMapEntry entry##in_name; \ -- cgit v1.2.1