From d6e85c3e9c5bbe44f38eb26475d3125e6c7fa76b Mon Sep 17 00:00:00 2001 From: Louis Stermole Date: Fri, 31 May 2019 15:58:41 -0400 Subject: Add reset of FORCE_STR to exp_draminit_mc Along with the corresponding update in exp_scominit, allows for the PHY to perform a read latency training step to assist with latency characterization and optimization. JIRA EDBC-439 Change-Id: Ie12d785b9f9f7739e1435e9875797d237cbf6f1c Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78190 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Reviewed-by: Mark Pizzutillo Reviewed-by: STEPHEN GLANCY Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78206 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- src/import/generic/memory/lib/utils/mc/gen_mss_port.H | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/import/generic') diff --git a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H index 94e3fa6bf..1e776b49e 100644 --- a/src/import/generic/memory/lib/utils/mc/gen_mss_port.H +++ b/src/import/generic/memory/lib/utils/mc/gen_mss_port.H @@ -293,6 +293,19 @@ fapi_try_exit: } +/// +/// @brief Change the state of the force_str bit +/// @tparam MC the memory controller type +/// @tparam T the fapi2 target type of the target +/// @tparam TT the class traits for the port +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T, typename TT = portTraits > +fapi2::ReturnCode change_force_str( const fapi2::Target& i_target, const states i_state ); + + /// /// @brief Change the state of the MC Refresh enable bit /// @tparam MC the memory controller type -- cgit v1.2.1