From 6a6d637366355b8c14ba53f83e2a14dade48135c Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Fri, 24 Aug 2018 13:51:23 -0500 Subject: Moves CAS latency algorithm to generic folder Change-Id: Ie2a7e7f7b1f1e0f78716d458531715016a539ec0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65187 Dev-Ready: STEPHEN GLANCY Tested-by: Jenkins Server Tested-by: HWSV CI Reviewed-by: Louis Stermole Reviewed-by: ANDRE A. MARIN Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65210 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes --- .../procedures/xml/error_info/generic_error.xml | 183 ++++++++++++++++++++- 1 file changed, 177 insertions(+), 6 deletions(-) (limited to 'src/import/generic/procedures') diff --git a/src/import/generic/procedures/xml/error_info/generic_error.xml b/src/import/generic/procedures/xml/error_info/generic_error.xml index 34aacaa28..57b6685c9 100644 --- a/src/import/generic/procedures/xml/error_info/generic_error.xml +++ b/src/import/generic/procedures/xml/error_info/generic_error.xml @@ -37,12 +37,166 @@ + + RC_MSS_EMPTY_VECTOR + + Empty vector conditional failed. + + RECEIVED + FUNCTION + + TARGET + MEDIUM + + + CODE + LOW + + + + + RC_MSS_FREQ_CL_EXCEEDS_TAA_MAX + + Calculated Cas Latency exceeds JEDEC value for TAA Max + desired (and DIMM supported) cas_latency * proposed tck from mss freq attributes > jedec taa_max + Probably due to MRW/ VPD freqs being too high + + CAS_LATENCY + TCK + TAA_MAX + COMPARE + IS_3DS + MC_TYPE + + CODE + HIGH + + + + PORT_TARGET + TARGET_TYPE_DIMM + + LOW + + + + + RC_MSS_FREQ_FAILED_TO_FIND_SUPPORTED_CL + + Desired CAS latency isn't supported in the common CAS latency bin retrieved from SPD. + + DESIRED_CAS_LATENCY + COMMON_CLS + TAA + TCK + MC_TYPE + + CODE + HIGH + + + + PORT_TARGET + TARGET_TYPE_DIMM + + MEDIUM + + + + PORT_TARGET + TARGET_TYPE_DIMM + + + + + PORT_TARGET + TARGET_TYPE_DIMM + + + + + + RC_MSS_FREQ_INVALID_CALCULATED_TCK + + Invalid value clock period (less than equal 0). + Should be code bug and error comparing MRW and VPD SUPPRTED_FREQS + Caused by bad MRW values for MSS_MRW_SUPPORTED_FREQ + + TAAMIN + PROPOSED_TCK + IS_3DS + MC_TYPE + + CODE + HIGH + + + + PORT_TARGET + TARGET_TYPE_DIMM + + MEDIUM + + + + + RC_MSS_FREQ_NO_COMMON_SUPPORTED_CL + + Current Configuration has no common supported CL values. + Caused by bad SPD on one of the plugged DIMMS + or DIMM configuration is not supported + + MC_TYPE + CL_SUPPORTED + + + PORT_TARGET + TARGET_TYPE_DIMM + + HIGH + + + + PORT_TARGET + TARGET_TYPE_DIMM + + + + + PORT_TARGET + TARGET_TYPE_DIMM + + + + + + RC_MSS_FREQ_SELECTED_FREQ_NOT_SUPPORTED + Selected freq based on calculations from the DIMM and VPD is not supported + SUPPORTED_FREQ_0 + SUPPORTED_FREQ_1 + SUPPORTED_FREQ_2 + SUPPORTED_FREQ_3 + FREQ + MC_TYPE + + CODE + HIGH + + + + TARGET + TARGET_TYPE_DIMM + + MEDIUM + + + - RC_MSS_INVALID_FREQUENCY + RC_MSS_INVALID_CLOCK_PERIOD - An invalid frequency was passed to frequency to clock period + An invalid clock period was passed to clock period to frequency - FREQ + CLOCK_PERIOD CODE HIGH @@ -50,15 +204,32 @@ - RC_MSS_INVALID_CLOCK_PERIOD + RC_MSS_INVALID_FREQUENCY - An invalid clock period was passed to clock period to frequency + An invalid frequency was passed to frequency to clock period - CLOCK_PERIOD + FREQ CODE HIGH + + RC_MSS_INVALID_TIMING_VALUE + Invalid value calculated for timing value based on MTB and FTB from SPD. + VALUE + FUNCTION + + DIMM_TARGET + HIGH + + + DIMM_TARGET + + + DIMM_TARGET + + + -- cgit v1.2.1