From bcecb8a2a15af6d4147a740d3fc4d4224b38fd93 Mon Sep 17 00:00:00 2001 From: "Christian R. Geddes" Date: Fri, 15 Mar 2019 17:13:02 -0500 Subject: Revert "Update phy_pharams structure, tests, and exp attrs" This reverts commit ee476c6abdade79afa5e3c989b58f4e1c21a42f9. Change-Id: I884ea3a8c7909403b0b15b3479e388c670e4d462 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/73467 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes --- .../attribute_info/generic_memory_attributes.xml | 509 ++++++++++++--------- .../generic_memory_eff_attributes.xml | 56 +++ .../generic_memory_si_attributes.xml | 175 ++----- 3 files changed, 381 insertions(+), 359 deletions(-) (limited to 'src/import/generic/procedures/xml/attribute_info') diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml index 348764642..d10983bdb 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_attributes.xml @@ -82,8 +82,7 @@ ATTR_MEM_VPD_DQ_MAP TARGET_TYPE_MEM_PORT - ARRAY[Dimm DQ PIN] - The map from the Dual Inline Memory Module + [Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to the Module Package Data (DQ) Pinout @@ -96,246 +95,306 @@ 72 - - ATTR_MEM_DIMM_DDR4_F0RC0F - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F0RC0F - Command Latency Adder Control Word; - Default value - 04. Values Range from 00 to 04. - No need to calculate; User can override with desired experimental value. - - - uint8 - - 2 - dimm_ddr4_f0rc0f - + + ATTR_MEM_GEARDOWN_MODE + TARGET_TYPE_MEM_PORT + + Gear Down Mode. + This is for DDR4 MRS3. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + + + uint8 + HALF =0, QUARTER=1 + + 2 + geardown_mode + - - ATTR_MEM_CS_CMD_LATENCY - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - CS to CMD/ADDR Latency. - This is for DDR4 MRS4. - Computed in mss_eff_cnfg. - Each memory channel will have a value. - - - uint8 - DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8 - - 2 - cs_cmd_latency - + + ATTR_MEM_DIMM_DDR4_F0RC0F + TARGET_TYPE_MEM_PORT + + F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + + uint8 + + 2 + dimm_ddr4_f0rc0f + - - ATTR_MEM_CA_PARITY_LATENCY - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - C/A Parity Latency Mode. This is for DDR4 MRS5. - Computed in mss_eff_cnfg. Each memory channel will have a value. - - - uint8 - DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8 - - 2 - ca_parity_latency - + + ATTR_MEM_CS_CMD_LATENCY + TARGET_TYPE_MEM_PORT + + CS to CMD/ADDR Latency. + This is for DDR4 MRS4. + Computed in mss_eff_cnfg. + Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + + + uint8 + DISABLE = 0, 3CYC = 3, 4CYC = 4, 5CYC = 5, 6CYC = 6, 8CYC = 8 + + 2 + cs_cmd_latency + - - ATTR_MEM_DIMM_DDR4_F0RC02 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F0RC02: Timing and IBT Control Word; Default value - 0x00. - Values Range from 0-8. No need to calculate; - User can override with desired experimental value. - - - uint8 - - 2 - dimm_ddr4_f0rc02 - + + ATTR_MEM_CA_PARITY_LATENCY + TARGET_TYPE_MEM_PORT + + C/A Parity Latency Mode. This is for DDR4 MRS5. + Computed in mss_eff_cnfg. Each memory channel will have a value. + creator: mss_eff_cnfg + consumer: various + firmware notes: none + + + uint8 + DISABLE = 0, PL4 = 4, PL5 = 5, PL6 = 6, PL8 = 8 + + 2 + ca_parity_latency + - - ATTR_MEM_DIMM_DDR4_F0RC03 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F0RC03 - CA and CS Signals Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. - Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. - - - uint8 - - 2 - dimm_ddr4_f0rc03 - + + ATTR_MEM_DIMM_DDR4_F0RC02 + TARGET_TYPE_MEM_PORT + + F0RC02: Timing and IBT Control Word; Default value - 0x00. + Values Range from 0-8. No need to calculate; + User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + + + uint8 + + 2 + dimm_ddr4_f0rc02 + - - ATTR_MEM_DIMM_DDR4_F0RC04 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). - Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. - - - uint8 - - 2 - dimm_ddr4_f0rc04 - + + ATTR_MEM_DIMM_DDR4_F0RC03 + TARGET_TYPE_MEM_PORT + + F0RC03 - CA and CS Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + + + uint8 + + 2 + dimm_ddr4_f0rc03 + - - ATTR_MEM_DIMM_DDR4_F0RC05 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F0RC05 - Clock Driver Characteristics Control Word; - Default value - 0x05 (Moderate Drive). - Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. - - - uint8 - - 2 - dimm_ddr4_f0rc05 - + + ATTR_MEM_DIMM_DDR4_F0RC04 + TARGET_TYPE_MEM_PORT + + F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + + + uint8 + + 2 + dimm_ddr4_f0rc04 + - - ATTR_MEM_DIMM_DDR4_F0RC0B - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - Operating Voltage VDD and VrefCA Source Control Word; - Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. - No need to calculate; User can override with desired experimental value. - - - uint8 - - 2 - dimm_ddr4_f0rc0b - + + ATTR_MEM_DIMM_DDR4_F0RC05 + TARGET_TYPE_MEM_PORT + + F0RC05 - Clock Driver Characteristics Control Word; + Default value - 0x05 (Moderate Drive). + Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none + + + uint8 + + 2 + dimm_ddr4_f0rc05 + - - ATTR_MEM_DIMM_DDR4_F0RC1X - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F0RC1x - Internal VrefCA Control Word; - Default value - 00. Values Range from 00 to 3F. - No need to calculate; User can override with desired experimental value. - + + ATTR_MEM_DIMM_DDR4_F0RC0B + TARGET_TYPE_MEM_PORT + Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none - uint8 - - 2 - dimm_ddr4_f0rc1x - + uint8 + + 2 + dimm_ddr4_f0rc0b + - - ATTR_MEM_DIMM_DDR4_F0RC7X - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F0RC7x: IBT Control Word; - Default value - 00. Values Range from 00 to FF.No need to calculate. - User can override with desired experimental value. - + + ATTR_MEM_DIMM_DDR4_F0RC1X + TARGET_TYPE_MEM_PORT + F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none - uint8 - - 2 - dimm_ddr4_f0rc7x - + uint8 + + 2 + dimm_ddr4_f0rc1x + - - ATTR_MEM_DIMM_DDR4_F1RC00 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word; - Default value - 00. Values Range from 00 to 0F. No need to calculate. - User can override with desired experimental value. - + + ATTR_MEM_DIMM_DDR4_F0RC7X + TARGET_TYPE_MEM_PORT + F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none - uint8 - - 2 - dimm_ddr4_f1rc00 - + uint8 + + 2 + dimm_ddr4_f0rc7x + - - ATTR_MEM_DIMM_DDR4_F1RC02 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word; - Default value - 00. Values Range from 00 to 0F. No need to calculate; - User can override with desired experimental value. - + + ATTR_MEM_DIMM_DDR4_F1RC00 + TARGET_TYPE_MEM_PORT + F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired experimental value. + creator: mss_eff_cnfg + consumer: mss_dram_init + firmware notes: none - uint8 - - 2 - dimm_ddr4_f1rc02 - + uint8 + + 2 + dimm_ddr4_f1rc00 + - - ATTR_MEM_DIMM_DDR4_F1RC03 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word. - Default value - 00. Values Range from 00 to 0F. No need to calculate. - User can override with desired experimental value. - - - uint8 - - 2 - dimm_ddr4_f1rc03 - + + ATTR_MEM_VREF_DQ_TRAIN_VALUE + TARGET_TYPE_MEM_PORT + + vrefdq_train value. This is for DDR4 MRS6. + Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none + + + uint8 + + 2 4 + vref_dq_train_value + - - ATTR_MEM_DIMM_DDR4_F1RC04 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word; - Default value - 00. Values Range from 00 to 0F. No need to calculate. - User can override with desired experimental value. - - - uint8 - - 2 - dimm_ddr4_f1rc04 - + + ATTR_MEM_VREF_DQ_TRAIN_RANGE + TARGET_TYPE_MEM_PORT + + vrefdq_train range. This is for DDR4 MRS6. + Computed in mss_eff_cnfg. Each memory channel will have a value. + Creator: mss_eff_cnfg + Consumer:various + Firmware notes: none + + + uint8 + RANGE1 = 0, RANGE2 = 1 + + 2 4 + vref_dq_train_range + - - ATTR_MEM_DIMM_DDR4_F1RC05 - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM] - F1RC00: Data Buffer Interface Driver Characteristics Control Word. - Default value - 00. Values Range from 00 to 0F. No need to calculate. - User can override with desired experimental value. - - - uint8 - - 2 - dimm_ddr4_f1rc05 - + + ATTR_MEM_PSTATES + TARGET_TYPE_MEM_PORT + + Number of p-states used + Always set NumPStates to 1 for Explorer. + + uint8 + + + pstates + + + + ATTR_MEM_BYTE_ENABLES + TARGET_TYPE_MEM_PORT + + Enable/Disable DBYTE macro (clock gating and IO tri-state) + 10-bit bitmap + Right aligned + + uint16 + + + byte_enables + + + + ATTR_MEM_NIBBLE_ENABLES + TARGET_TYPE_MEM_PORT + + Account/Ignore training/dfi_bist result on the selected nibble. + 20-bit bitmap + Right aligned + + uint32 + + + nibble_enables + + + + ATTR_MEM_TAA_MIN + TARGET_TYPE_MEM_PORT + + Timing value used to calculate CAS Latency + + + uint8 + + nck + taa_min + + + + ATTR_MEM_RANK_FOUR_MODE + TARGET_TYPE_MEM_PORT + + DIMM Rank 4 mode enable + + uint8 + DISABLE = 0, ENABLE = 1 + + + rank4_mode + diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml index cec393f11..b34019c60 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_eff_attributes.xml @@ -787,4 +787,60 @@ volt_vpp + + ATTR_MEM_EFF_MRAM_SUPPORT + TARGET_TYPE_MEM_PORT + + Supports MRAM or not + + uint8 + + NORMAL = 0, EVERSPIN = 1 + + mram_support + + + + ATTR_MEM_EFF_3DS_HEIGHT + TARGET_TYPE_MEM_PORT + + ARRAY[DIMM] + Primary SDRAM Package Type. + Decodes Byte 6. + This byte defines the primary set of SDRAMs. + Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = 3DS + + uint8 + + PLANAR = 0, H2 = 2, H4 = 4, H8 = 8 + + 3ds_height + + + + ATTR_MEM_EFF_DDP_COMPATIBLE + TARGET_TYPE_MEM_PORT + + DDP Compatibility + + uint8 + + DISABLE = 0, ENABLE = 1 + + ddp_compatibility + + + + ATTR_MEM_EFF_TSV8H_SUPPORT + TARGET_TYPE_MEM_PORT + + TSVH8 Support + + uint8 + + DISABLE = 0, ENABLE = 1 + + tsv8h_support + + diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml index 819336678..008a90974 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_si_attributes.xml @@ -100,8 +100,7 @@ ATTR_MEM_SI_DRAM_DRV_IMP_DQ_DQS TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - DQ and DQS Drive Impedance. + Array[DIMM][RANK] DQ and DQS Drive Impedance. uint8 @@ -116,10 +115,9 @@ ATTR_MEM_SI_DRAM_PREAMBLE TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. - The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. - E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE + Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. + The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, and Bit 7 for WRITE preamble. + E.g. 0b00010001 means 2 nCK preamble for both READ and WRITE uint8 @@ -127,15 +125,13 @@ READ_PREAMBLE_BIT = 3, WRITE_PREAMBLE_BIT = 7 nCK si_dram_preamble - 2 4 ATTR_MEM_SI_DRAM_RTT_NOM TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - DRAM side Nominal Termination Resistance in Ohms. + Array[DIMM][RANK] DRAM side Nominal Termination Resistance in Ohms. uint8 @@ -150,8 +146,7 @@ ATTR_MEM_SI_DRAM_RTT_PARK TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - DRAM side Park Termination Resistance in Ohms. + Array[DIMM][RANK] DRAM side Park Termination Resistance in Ohms. uint8 @@ -166,8 +161,7 @@ ATTR_MEM_SI_DRAM_RTT_WR TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - DRAM side Write Termination Resistance in Ohms. + Array[DIMM][RANK] DRAM side Write Termination Resistance in Ohms. uint8 @@ -178,102 +172,24 @@ 2 4 - - ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM][RANK] - vrefdq_train value. This is for DDR4 MRS6. - - - uint8 - - 2 4 - si_vref_dq_train_value - - - - ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM][RANK] - vrefdq_train range. This is for DDR4 MRS6. - - - uint8 - RANGE1 = 0, RANGE2 = 1 - - 2 4 - si_vref_dq_train_range - - - - ATTR_MEM_SI_GEARDOWN_MODE - TARGET_TYPE_MEM_PORT - - ARRAY[DIMM][RANK] - Gear Down Mode. - This is for DDR4 MRS3. - Each memory channel will have a value. - - - uint8 - HALF =0, QUARTER=1 - - 2 4 - si_geardown_mode - - - - ATTR_MEM_SI_MC_DRV_DQ_DQS - TARGET_TYPE_MEM_PORT - - Array[DIMM][RANK] - Tx drive impedance for DQ/DQS of all ranks in ohms - - - uint8 - - si_mc_drv_dq_dqs - 2 4 - - - - ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS - TARGET_TYPE_MEM_PORT - - Array[DIMM][RANK] - Memory Controller side Receiver Equalization for Data and Data Strobe Lines. - - - uint8 - - DISABLE = 0, ENABLE = 1 - si_mc_rcv_eq_dq_dqs - 2 4 - - ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Equalization for Data and Data Strobe Lines. + Memory Controller side Drive Equalization for Data and Data Strobe Lines. uint8 DISABLE = 0, FFE = 1 si_mc_drv_eq_dq_dqs - 2 4 ATTR_MEM_SI_MC_DRV_IMP_CLK TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Impedance for Clock in Ohms. + Memory Controller side Drive Impedance for Clock in Ohms. uint8 @@ -281,15 +197,13 @@ DISABLE = 0 ohm si_mc_drv_imp_clk - 2 4 ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. + Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and Activate Lines in Ohms. uint8 @@ -297,15 +211,13 @@ DISABLE = 0 ohm si_mc_drv_imp_cmd_addr - 2 4 ATTR_MEM_SI_MC_DRV_IMP_CNTL TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. + Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset Lines in Ohms. uint8 @@ -313,15 +225,13 @@ DISABLE = 0 ohm si_mc_drv_imp_cntl - 2 4 ATTR_MEM_SI_MC_DRV_IMP_CSCID TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. + Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. uint8 @@ -329,15 +239,13 @@ DISABLE = 0 ohm si_mc_drv_imp_cscid - 2 4 ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Impedance Pull Down for Data and Data Strobe Lines in Ohms. + Array[PSTATE] Memory Controller side Drive Impedance Pull Down for Data and Data Strobe Lines in Ohms. uint8 @@ -345,15 +253,14 @@ DISABLE = 0 ohm si_mc_drv_imp_dq_dqs_pull_down - 2 4 + 1 ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Impedance Pull Up for Data and Data Strobe Lines in Ohms. + Array[PSTATE] Memory Controller side Drive Impedance Pull Up for Data and Data Strobe Lines in Ohms. uint8 @@ -361,15 +268,14 @@ DISABLE = 0 ohm si_mc_drv_imp_dq_dqs_pull_up - 2 4 + 1 ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Clock in Ohms. + Memory Controller side Drive Slew Rate for Clock in Ohms. uint8 @@ -377,15 +283,13 @@ DISABLE = 0 ohm si_mc_drv_slew_rate_clk - 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and Activate Lines in Ohms. + Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and Activate Lines in Ohms. uint8 @@ -393,15 +297,13 @@ DISABLE = 0 ohm si_mc_drv_slew_rate_cmd_addr - 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset Lines in Ohms. + Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset Lines in Ohms. uint8 @@ -409,15 +311,13 @@ DISABLE = 0 ohm si_mc_drv_slew_rate_cntl - 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. + Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. uint8 @@ -425,15 +325,13 @@ DISABLE = 0 ohm si_mc_drv_slew_rate_cscid - 2 4 ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Drive Slew Rate for Data and Data Strobe Lines in Ohms. + Array[PSTATE] Memory Controller side Drive Slew Rate for Data and Data Strobe Lines in Ohms. uint8 @@ -441,7 +339,20 @@ DISABLE = 0 ohm si_mc_drv_slew_rate_dq_dqs - 2 4 + 1 + + + + ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS + TARGET_TYPE_MEM_PORT + + Memory Controller side Receiver Equalization for Data and Data Strobe Lines. + + + uint8 + + DISABLE = 0, DFE = 1 + si_mc_rcv_eq_dq_dqs @@ -456,15 +367,13 @@ DISABLE = 0 ohm si_mc_rcv_imp_alert_n - 2 4 ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - Memory Controller side Receiver Impedance. Data and Data Strobe Lines in Ohms. + Array[PSTATE] Memory Controller side Receiver Impedance. Data and Data Strobe Lines in Ohms. uint8 @@ -472,16 +381,15 @@ DISABLE = 0 ohm si_mc_rcv_imp_dq_dqs - 2 4 + 1 ATTR_MEM_SI_ODT_RD TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. - The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] + Array[DIMM][RANK] READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. + The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] uint8 @@ -494,9 +402,8 @@ ATTR_MEM_SI_ODT_WR TARGET_TYPE_MEM_PORT - Array[DIMM][RANK] - WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. - The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] + Array[DIMM][RANK] WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT to fire for the designated rank. + The bits in 8 bit field are [Dimm0 ODT0][Dimm0 ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 ODT1][N/A][N/A] uint8 -- cgit v1.2.1