From 1061da0271bf85fe29fedff6f242181b3dc6d5ed Mon Sep 17 00:00:00 2001 From: Andre Marin Date: Thu, 11 Jul 2019 13:01:31 -0400 Subject: Add missing attributes needed to be set for generic mss_kind Setting DRAM_MFG_ID, RCD_MFG_ID, and MODULE_HEIGHT to eff_config and editing SPD timing values to use common API for calculations that come with values from the EEPROM Change-Id: If33f2f2a49a62f114575ef36d6325fc537d1dc27 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79921 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Louis Stermole Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79936 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M Crowell --- src/import/generic/memory/lib/spd/spd_fields_ddr4.H | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/import/generic/memory/lib/spd/spd_fields_ddr4.H') diff --git a/src/import/generic/memory/lib/spd/spd_fields_ddr4.H b/src/import/generic/memory/lib/spd/spd_fields_ddr4.H index 6739276cb..194eba510 100644 --- a/src/import/generic/memory/lib/spd/spd_fields_ddr4.H +++ b/src/import/generic/memory/lib/spd/spd_fields_ddr4.H @@ -1176,6 +1176,12 @@ class fields PMIC1_PHASE_COMBIN_BYTE = 259, PMIC1_PHASE_COMBIN_START = 4, PMIC1_PHASE_COMBIN_LEN = 4, + + // Byte 552-553 + DRAM_MFR_ID_CODE_LSB_BYTE = 552, + DRAM_MFR_ID_CODE_MSB_BYTE = 553, + DRAM_MFR_ID_CODE_START = 0, + DRAM_MFR_ID_CODE_LEN = 8, }; public: @@ -1408,6 +1414,9 @@ class fields // Byte 259: PMIC1 Phase Combination static constexpr field_t PMIC1_PHASE_COMBIN{PMIC1_PHASE_COMBIN_BYTE, PMIC1_PHASE_COMBIN_START, PMIC1_PHASE_COMBIN_LEN}; + // Byte 552 and 553: DRAM manufacturing ID for DDIMMs + static constexpr field_t DRAM_MFR_ID_CODE_LSB{DRAM_MFR_ID_CODE_LSB_BYTE, DRAM_MFR_ID_CODE_START, DRAM_MFR_ID_CODE_LEN}; + static constexpr field_t DRAM_MFR_ID_CODE_MSB{DRAM_MFR_ID_CODE_MSB_BYTE, DRAM_MFR_ID_CODE_START, DRAM_MFR_ID_CODE_LEN}; }; }// spd -- cgit v1.2.1