From c368037cb36e1e2907c96bb9be66a5cc80542b6f Mon Sep 17 00:00:00 2001 From: "Andre A. Marin" Date: Tue, 5 Mar 2019 22:53:02 -0600 Subject: Update phy_pharams structure, tests, and exp attrs Change-Id: Ie84463e9497bf53d8cd13b14526be93d9de95506 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72070 Tested-by: FSP CI Jenkins Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: HWSV CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Louis Stermole Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72086 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../memory/lib/mss_generic_attribute_getters.H | 1201 +++++++++++++------- 1 file changed, 784 insertions(+), 417 deletions(-) (limited to 'src/import/generic/memory/lib/mss_generic_attribute_getters.H') diff --git a/src/import/generic/memory/lib/mss_generic_attribute_getters.H b/src/import/generic/memory/lib/mss_generic_attribute_getters.H index dc22d4fb0..bce94f55f 100644 --- a/src/import/generic/memory/lib/mss_generic_attribute_getters.H +++ b/src/import/generic/memory/lib/mss_generic_attribute_getters.H @@ -83,8 +83,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note [Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin to -/// the Module Package Data (DQ) Pinout +/// @note ARRAY[Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) Pin +/// to the Module Package Data (DQ) Pinout /// inline fapi2::ReturnCode get_mem_vpd_dq_map(const fapi2::Target& i_target, uint8_t (&o_array)[72]) @@ -101,63 +101,15 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief ATTR_MEM_GEARDOWN_MODE getter -/// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel -/// will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none -/// -inline fapi2::ReturnCode get_geardown_mode(const fapi2::Target& i_target, uint8_t& o_value) -{ - uint8_t l_value[2] = {}; - const auto l_port = i_target.getParent(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_GEARDOWN_MODE, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_GEARDOWN_MODE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_GEARDOWN_MODE getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t&[] array reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Gear Down Mode. This is for DDR4 MRS3. Computed in mss_eff_cnfg. Each memory channel -/// will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none -/// -inline fapi2::ReturnCode get_geardown_mode(const fapi2::Target& i_target, - uint8_t (&o_array)[2]) -{ - uint8_t l_value[2] = {}; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_GEARDOWN_MODE, i_target, l_value) ); - memcpy(o_array, &l_value, 2); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_GEARDOWN_MODE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - /// /// @brief ATTR_MEM_DIMM_DDR4_F0RC0F getter /// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from -/// 00 to 04. No need to calculate; User can override with desired experimental value. -/// creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC0F - Command Latency Adder Control Word; Default value - 04. Values +/// Range from 00 to 04. No need to calculate; User can override with desired experimental +/// value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target& i_target, uint8_t& o_value) { @@ -180,9 +132,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from -/// 00 to 04. No need to calculate; User can override with desired experimental value. -/// creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC0F - Command Latency Adder Control Word; Default value - 04. Values +/// Range from 00 to 04. No need to calculate; User can override with desired experimental +/// value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc0f(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -205,9 +157,8 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: -/// none +/// @note ARRAY[DIMM] CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. +/// Each memory channel will have a value. /// inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target& i_target, uint8_t& o_value) { @@ -230,9 +181,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: -/// none +/// @note ARRAY[DIMM] CS to CMD/ADDR Latency. This is for DDR4 MRS4. Computed in mss_eff_cnfg. +/// Each memory channel will have a value. /// inline fapi2::ReturnCode get_cs_cmd_latency(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -255,9 +205,8 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: -/// none +/// @note ARRAY[DIMM] C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. +/// Each memory channel will have a value. /// inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target& i_target, uint8_t& o_value) { @@ -280,9 +229,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: -/// none +/// @note ARRAY[DIMM] C/A Parity Latency Mode. This is for DDR4 MRS5. Computed in mss_eff_cnfg. +/// Each memory channel will have a value. /// inline fapi2::ReturnCode get_ca_parity_latency(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -305,9 +253,8 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. -/// No need to calculate; User can override with desired experimental value. creator: -/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range +/// from 0-8. No need to calculate; User can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target& i_target, uint8_t& o_value) { @@ -330,9 +277,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. -/// No need to calculate; User can override with desired experimental value. creator: -/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range +/// from 0-8. No need to calculate; User can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc02(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -355,10 +301,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - -/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD -/// byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// @note ARRAY[DIMM] F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default +/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from +/// SPD byte 137, 1st Nibble for CS and CA. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target& i_target, uint8_t& o_value) { @@ -381,10 +326,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - -/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD -/// byte 137, 1st Nibble for CS and CA. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// @note ARRAY[DIMM] F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default +/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from +/// SPD byte 137, 1st Nibble for CS and CA. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc03(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -407,10 +351,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value -/// - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD -/// byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// @note ARRAY[DIMM] F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default +/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from +/// SPD byte 137, 2nd Nibble for ODT and CKE. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target& i_target, uint8_t& o_value) { @@ -433,10 +376,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value -/// - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD -/// byte 137, 2nd Nibble for ODT and CKE. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// @note ARRAY[DIMM] F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default +/// value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from +/// SPD byte 137, 2nd Nibble for ODT and CKE. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc04(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -459,9 +401,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate -/// Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble -/// for CK. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC05 - Clock Driver Characteristics Control Word; Default value - +/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 138, 2nd Nibble for CK. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target& i_target, uint8_t& o_value) { @@ -484,9 +426,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate -/// Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble -/// for CK. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC05 - Clock Driver Characteristics Control Word; Default value - +/// 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD +/// byte 138, 2nd Nibble for CK. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc05(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -509,10 +451,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. +/// @note ARRAY[DIMM] Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. /// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User -/// can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target& i_target, uint8_t& o_value) { @@ -535,10 +476,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. +/// @note ARRAY[DIMM] Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT_VDDR. /// Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User -/// can override with desired experimental value. creator: mss_eff_cnfg consumer: mss_dram_init -/// firmware notes: none +/// can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc0b(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -561,9 +501,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 -/// to 3F.No need to calculate; User can override with desired experimental value. creator: -/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range +/// from 00 to 3F. No need to calculate; User can override with desired experimental +/// value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target& i_target, uint8_t& o_value) { @@ -586,9 +526,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 -/// to 3F.No need to calculate; User can override with desired experimental value. creator: -/// mss_eff_cnfg consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range +/// from 00 to 3F. No need to calculate; User can override with desired experimental +/// value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc1x(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -611,9 +551,8 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need -/// to calculate; User can override with desired experimental value. creator: mss_eff_cnfg -/// consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to +/// FF.No need to calculate. User can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target& i_target, uint8_t& o_value) { @@ -636,9 +575,8 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need -/// to calculate; User can override with desired experimental value. creator: mss_eff_cnfg -/// consumer: mss_dram_init firmware notes: none +/// @note ARRAY[DIMM] F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to +/// FF.No need to calculate. User can override with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f0rc7x(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -661,10 +599,9 @@ fapi_try_exit: /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value -/// - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired -/// experimental value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target& i_target, uint8_t& o_value) { @@ -687,10 +624,9 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default value -/// - 00. Values Range from 00 to 0F.No need to calculate; User can override with desired -/// experimental value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// inline fapi2::ReturnCode get_dimm_ddr4_f1rc00(const fapi2::Target& i_target, uint8_t (&o_array)[2]) @@ -708,205 +644,201 @@ fapi_try_exit: } /// -/// @brief ATTR_MEM_VREF_DQ_TRAIN_VALUE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC02 getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value +/// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate; User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_vref_dq_train_value(const fapi2::Target& i_target, - uint8_t (&o_array)[4]) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc02(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2][4] = {}; + uint8_t l_value[2] = {}; const auto l_port = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_VALUE, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC02, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC02: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_VREF_DQ_TRAIN_VALUE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC02 getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note vrefdq_train value. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate; User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_vref_dq_train_value(const fapi2::Target& i_target, - uint8_t (&o_array)[2][4]) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc02(const fapi2::Target& i_target, + uint8_t (&o_array)[2]) { - uint8_t l_value[2][4] = {}; + uint8_t l_value[2] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_VALUE, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC02, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC02: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_VREF_DQ_TRAIN_RANGE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC03 getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t&[] array reference to store the value +/// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_vref_dq_train_range(const fapi2::Target& i_target, - uint8_t (&o_array)[4]) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc03(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2][4] = {}; + uint8_t l_value[2] = {}; const auto l_port = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_RANGE, l_port, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC03, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC03: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_VREF_DQ_TRAIN_RANGE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC03 getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note vrefdq_train range. This is for DDR4 MRS6. Computed in mss_eff_cnfg. Each memory -/// channel will have a value. Creator: mss_eff_cnfg Consumer:various Firmware notes: -/// none +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_vref_dq_train_range(const fapi2::Target& i_target, - uint8_t (&o_array)[2][4]) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc03(const fapi2::Target& i_target, + uint8_t (&o_array)[2]) { - uint8_t l_value[2][4] = {}; + uint8_t l_value[2] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_VREF_DQ_TRAIN_RANGE, i_target, l_value) ); - memcpy(o_array, &l_value, 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC03, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC03: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_PSTATES getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @brief ATTR_MEM_DIMM_DDR4_F1RC04 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Number of p-states used Always set NumPStates to 1 for Explorer. -/// -inline fapi2::ReturnCode get_pstates(const fapi2::Target& i_target, uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_PSTATES, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_PSTATES: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_BYTE_ENABLES getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint16_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Enable/Disable DBYTE macro (clock gating and IO tri-state) 10-bit bitmap Right aligned +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_byte_enables(const fapi2::Target& i_target, uint16_t& o_value) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc04(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_BYTE_ENABLES, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC04, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_BYTE_ENABLES: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC04: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_NIBBLE_ENABLES getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC04 getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint32_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Account/Ignore training/dfi_bist result on the selected nibble. 20-bit bitmap Right -/// aligned +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word; Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_nibble_enables(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc04(const fapi2::Target& i_target, + uint8_t (&o_array)[2]) { + uint8_t l_value[2] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_NIBBLE_ENABLES, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC04, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_NIBBLE_ENABLES: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC04: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_TAA_MIN getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @brief ATTR_MEM_DIMM_DDR4_F1RC05 getter +/// @param[in] const ref to the TARGET_TYPE_DIMM /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Timing value used to calculate CAS Latency +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_taa_min(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc05(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2] = {}; + const auto l_port = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_TAA_MIN, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC05, l_port, l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_TAA_MIN: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC05: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_RANK_FOUR_MODE getter +/// @brief ATTR_MEM_DIMM_DDR4_F1RC05 getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DIMM Rank 4 mode enable +/// @note ARRAY[DIMM] F1RC00: Data Buffer Interface Driver Characteristics Control Word. Default +/// value - 00. Values Range from 00 to 0F. No need to calculate. User can override +/// with desired experimental value. /// -inline fapi2::ReturnCode get_rank4_mode(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode get_dimm_ddr4_f1rc05(const fapi2::Target& i_target, + uint8_t (&o_array)[2]) { + uint8_t l_value[2] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_RANK_FOUR_MODE, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_DDR4_F1RC05, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_RANK_FOUR_MODE: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_DIMM_DDR4_F1RC05: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } @@ -2503,89 +2435,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief ATTR_MEM_EFF_MRAM_SUPPORT getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Supports MRAM or not -/// -inline fapi2::ReturnCode get_mram_support(const fapi2::Target& i_target, uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_MRAM_SUPPORT, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_EFF_MRAM_SUPPORT: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_EFF_3DS_HEIGHT getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ARRAY[DIMM] Primary SDRAM Package Type. Decodes Byte 6. This byte defines the primary -/// set of SDRAMs. Monolithic = SPD, Multi-load stack = DDP/QDP, Single-load stack = -/// 3DS -/// -inline fapi2::ReturnCode get_3ds_height(const fapi2::Target& i_target, uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_3DS_HEIGHT, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_EFF_3DS_HEIGHT: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_EFF_DDP_COMPATIBLE getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DDP Compatibility -/// -inline fapi2::ReturnCode get_ddp_compatibility(const fapi2::Target& i_target, - uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DDP_COMPATIBLE, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_EFF_DDP_COMPATIBLE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MEM_EFF_TSV8H_SUPPORT getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note TSVH8 Support -/// -inline fapi2::ReturnCode get_tsv8h_support(const fapi2::Target& i_target, uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_TSV8H_SUPPORT, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_EFF_TSV8H_SUPPORT: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - /// /// @brief ATTR_MEM_EFF_VOLT_VDDR getter @@ -2893,23 +2742,53 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_SI_DRAM_PREAMBLE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Number of clocks used for read/write preamble. Calibration only +/// uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. +/// The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit +/// 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK preamble +/// for both READ and WRITE +/// +inline fapi2::ReturnCode get_si_dram_preamble(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_DRAM_PREAMBLE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_SI_DRAM_PREAMBLE getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Number of clocks used for read/write preamble. Calibration only uses 1 nCK preamble -/// (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value of "0" means -/// 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for READ preamble, -/// and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK preamble for both READ -/// and WRITE +/// @note Array[DIMM][RANK] Number of clocks used for read/write preamble. Calibration only +/// uses 1 nCK preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. +/// The value of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit +/// 3 for READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK preamble +/// for both READ and WRITE /// inline fapi2::ReturnCode get_si_dram_preamble(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_DRAM_PREAMBLE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3060,129 +2939,504 @@ fapi_try_exit: } /// -/// @brief ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Equalization for Data and Data Strobe Lines. +/// @note ARRAY[DIMM][RANK] vrefdq_train value. This is for DDR4 MRS6. /// -inline fapi2::ReturnCode get_si_mc_drv_eq_dq_dqs(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode get_si_vref_dq_train_value(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) { + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_SI_MC_DRV_IMP_CLK getter +/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock in Ohms. +/// @note ARRAY[DIMM][RANK] vrefdq_train value. This is for DDR4 MRS6. /// -inline fapi2::ReturnCode get_si_mc_drv_imp_clk(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode get_si_vref_dq_train_value(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_VALUE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and -/// Activate Lines in Ohms. +/// @note ARRAY[DIMM][RANK] vrefdq_train range. This is for DDR4 MRS6. /// -inline fapi2::ReturnCode get_si_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode get_si_vref_dq_train_range(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) { + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_SI_MC_DRV_IMP_CNTL getter +/// @brief ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset -/// Lines in Ohms. +/// @note ARRAY[DIMM][RANK] vrefdq_train range. This is for DDR4 MRS6. /// -inline fapi2::ReturnCode get_si_mc_drv_imp_cntl(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode get_si_vref_dq_train_range(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CNTL, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CNTL: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_SI_VREF_DQ_TRAIN_RANGE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_SI_MC_DRV_IMP_CSCID getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @brief ATTR_MEM_SI_GEARDOWN_MODE getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in Ohms. +/// @note ARRAY[DIMM][RANK] Gear Down Mode. This is for DDR4 MRS3. Each memory channel will +/// have a value. /// -inline fapi2::ReturnCode get_si_mc_drv_imp_cscid(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode get_si_geardown_mode(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) { + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CSCID, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_GEARDOWN_MODE, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_SI_GEARDOWN_MODE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN getter -/// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @brief ATTR_MEM_SI_GEARDOWN_MODE getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Impedance Pull Down for Data and Data -/// Strobe Lines in Ohms. +/// @note ARRAY[DIMM][RANK] Gear Down Mode. This is for DDR4 MRS3. Each memory channel will +/// have a value. +/// +inline fapi2::ReturnCode get_si_geardown_mode(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_GEARDOWN_MODE, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_GEARDOWN_MODE: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Tx drive impedance for DQ/DQS of all ranks in ohms +/// +inline fapi2::ReturnCode get_si_mc_drv_dq_dqs(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_DQ_DQS, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Tx drive impedance for DQ/DQS of all ranks in ohms +/// +inline fapi2::ReturnCode get_si_mc_drv_dq_dqs(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_DQ_DQS, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Receiver Equalization for Data and Data +/// Strobe Lines. +/// +inline fapi2::ReturnCode get_si_mc_rcv_eq_dq_dqs(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Receiver Equalization for Data and Data +/// Strobe Lines. +/// +inline fapi2::ReturnCode get_si_mc_rcv_eq_dq_dqs(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Equalization for Data and Data Strobe +/// Lines. +/// +inline fapi2::ReturnCode get_si_mc_drv_eq_dq_dqs(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Equalization for Data and Data Strobe +/// Lines. +/// +inline fapi2::ReturnCode get_si_mc_drv_eq_dq_dqs(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_EQ_DQ_DQS: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CLK getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_clk(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CLK getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_clk(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CLK, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Address, Bank Address, +/// Bank Group and Activate Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Address, Bank Address, +/// Bank Group and Activate Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CNTL getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock Enable, ODT, +/// Parity, and Reset Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cntl(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CNTL, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CNTL: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CNTL getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Clock Enable, ODT, +/// Parity, and Reset Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cntl(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CNTL, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CNTL: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CSCID getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Chip Select and Chip +/// ID Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cscid(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CSCID, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_CSCID getter +/// @param[in] const ref to the TARGET_TYPE_MEM_PORT +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance for Chip Select and Chip +/// ID Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_imp_cscid(const fapi2::Target& i_target, + uint8_t (&o_array)[2][4]) +{ + uint8_t l_value[2][4] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_CSCID, i_target, l_value) ); + memcpy(o_array, &l_value, 8); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Down for Data and +/// Data Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_down(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; const auto l_port = i_target.getParent(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -3197,16 +3451,16 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Impedance Pull Down for Data and Data -/// Strobe Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Down for Data and +/// Data Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_down(const fapi2::Target& i_target, - uint8_t (&o_array)[1]) + uint8_t (&o_array)[2][4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN, i_target, l_value) ); - memcpy(o_array, &l_value, 1); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3218,20 +3472,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Impedance Pull Up for Data and Data Strobe -/// Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Up for Data and Data +/// Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_up(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; const auto l_port = i_target.getParent(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -3246,16 +3500,16 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Impedance Pull Up for Data and Data Strobe -/// Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Impedance Pull Up for Data and Data +/// Strobe Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_imp_dq_dqs_pull_up(const fapi2::Target& i_target, - uint8_t (&o_array)[1]) + uint8_t (&o_array)[2][4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_IMP_DQ_DQS_PULL_UP, i_target, l_value) ); - memcpy(o_array, &l_value, 1); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3264,19 +3518,45 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_slew_rate_clk(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Slew Rate for Clock in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_clk(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CLK, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3285,20 +3565,47 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Address, Bank Address, +/// Bank Group and Activate Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cmd_addr(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Slew Rate for Address, Bank Address, Bank Group and -/// Activate Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Address, Bank Address, +/// Bank Group and Activate Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cmd_addr(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CMD_ADDR, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3307,20 +3614,47 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock Enable, ODT, +/// Parity, and Reset Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cntl(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Slew Rate for Clock Enable, ODT, Parity, and Reset -/// Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Clock Enable, ODT, +/// Parity, and Reset Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cntl(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CNTL, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3329,19 +3663,47 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Chip Select and Chip +/// ID Lines in Ohms. +/// +inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cscid(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) +{ + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed getting ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Slew Rate for Chip Select and Chip ID Lines in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Chip Select and Chip +/// ID Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_cscid(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_CSCID, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3353,20 +3715,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Slew Rate for Data and Data Strobe Lines -/// in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Data and Data Strobe +/// Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_dq_dqs(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; const auto l_port = i_target.getParent(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -3381,16 +3743,16 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Drive Slew Rate for Data and Data Strobe Lines -/// in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Drive Slew Rate for Data and Data Strobe +/// Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_drv_slew_rate_dq_dqs(const fapi2::Target& i_target, - uint8_t (&o_array)[1]) + uint8_t (&o_array)[2][4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_DRV_SLEW_RATE_DQ_DQS, i_target, l_value) ); - memcpy(o_array, &l_value, 1); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3400,22 +3762,25 @@ fapi_try_exit: } /// -/// @brief ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS getter -/// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @brief ATTR_MEM_SI_MC_RCV_IMP_ALERT_N getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Receiver Equalization for Data and Data Strobe Lines. +/// @note Memory Controller side Receiver Impedance. Alert_N line in Ohms. /// -inline fapi2::ReturnCode get_si_mc_rcv_eq_dq_dqs(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode get_si_mc_rcv_imp_alert_n(const fapi2::Target& i_target, + uint8_t (&o_array)[4]) { + uint8_t l_value[2][4] = {}; + const auto l_port = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, l_port, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed getting ATTR_MEM_SI_MC_RCV_EQ_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed getting ATTR_MEM_SI_MC_RCV_IMP_ALERT_N: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } @@ -3423,16 +3788,18 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_RCV_IMP_ALERT_N getter /// @param[in] const ref to the TARGET_TYPE_MEM_PORT -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// @note Memory Controller side Receiver Impedance. Alert_N line in Ohms. /// inline fapi2::ReturnCode get_si_mc_rcv_imp_alert_n(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[2][4]) { + uint8_t l_value[2][4] = {}; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_ALERT_N, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: @@ -3444,20 +3811,20 @@ fapi_try_exit: /// /// @brief ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS getter /// @param[in] const ref to the TARGET_TYPE_DIMM -/// @param[out] uint8_t& reference to store the value +/// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Receiver Impedance. Data and Data Strobe Lines -/// in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Receiver Impedance. Data and Data Strobe +/// Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_rcv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t& o_value) + uint8_t (&o_array)[4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; const auto l_port = i_target.getParent(); FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS, l_port, l_value) ); - o_value = l_value[mss::index(i_target)]; + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: @@ -3472,16 +3839,16 @@ fapi_try_exit: /// @param[out] uint8_t&[] array reference to store the value /// @note Generated by gen_accessors.pl generate_mc_port_params /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Array[PSTATE] Memory Controller side Receiver Impedance. Data and Data Strobe Lines -/// in Ohms. +/// @note Array[DIMM][RANK] Memory Controller side Receiver Impedance. Data and Data Strobe +/// Lines in Ohms. /// inline fapi2::ReturnCode get_si_mc_rcv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t (&o_array)[1]) + uint8_t (&o_array)[2][4]) { - uint8_t l_value[1] = {}; + uint8_t l_value[2][4] = {}; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_MC_RCV_IMP_DQ_DQS, i_target, l_value) ); - memcpy(o_array, &l_value, 1); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: -- cgit v1.2.1