From d9bbcfabbc2f041ba85095ac70dc27c37cb87755 Mon Sep 17 00:00:00 2001 From: Louis Stermole Date: Fri, 7 Jun 2019 15:44:22 -0400 Subject: Add missing timing attrs to p9a_eff_config Change-Id: I0270bec76fa1146c3c74cc125f838f5602b8a5b8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78564 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Mark Pizzutillo Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78576 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../lib/data_engine/data_engine_traits_def.H | 29 ++++++++++++++++------ 1 file changed, 22 insertions(+), 7 deletions(-) (limited to 'src/import/generic/memory/lib/data_engine/data_engine_traits_def.H') diff --git a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H index 911821b5f..702e0db9a 100644 --- a/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H +++ b/src/import/generic/memory/lib/data_engine/data_engine_traits_def.H @@ -93,13 +93,28 @@ enum attr_eff_engine_fields ATTR_EFF_BASE_CASE = 0, // Attrs to set - DRAM_WIDTH = 1, - PRIM_BUS_WIDTH = 2, - DRAM_DENSITY = 3, - PRIMARY_DIE_COUNT = 4, - PRIM_STACK_TYPE = 5, - COLUMN_ADDR_BITS = 6, - ROW_ADDR_BITS = 7, + DRAM_CWL = 1, + DRAM_TREFI = 2, + DRAM_TCCD_L = 3, + DRAM_TWTR_L = 4, + DRAM_TWTR_S = 5, + DRAM_TFAW = 6, + DRAM_TRCD = 7, + DRAM_TRP = 8, + DRAM_TRAS = 9, + DRAM_TWR = 10, + DRAM_TRTP = 11, + DRAM_TRRD_S = 12, + DRAM_TRRD_L = 13, + DRAM_TRFC = 14, + DRAM_TRFC_DLR = 15, + DRAM_WIDTH = 16, + PRIM_BUS_WIDTH = 17, + DRAM_DENSITY = 18, + PRIMARY_DIE_COUNT = 19, + PRIM_STACK_TYPE = 20, + COLUMN_ADDR_BITS = 21, + ROW_ADDR_BITS = 22, // Dispatcher set to last enum value ATTR_EFF_DISPATCHER = ROW_ADDR_BITS, -- cgit v1.2.1