From 73ab4c0fbad5df678d3ccad9982066f4ab62fcb1 Mon Sep 17 00:00:00 2001 From: Brian Silver Date: Wed, 30 Dec 2015 09:03:10 -0600 Subject: Added mss::get/putScom Change-Id: I1bb2ae73d4c90c771a285b292b04b566e302fafc Original-Change-Id: Ib6571e6e9e374c6d8995235e2553bce149b0113b Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22988 Tested-by: Jenkins Server Reviewed-by: Craig C. Hamilton Reviewed-by: Christian Geddes Reviewed-by: Brian Silver Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22760 Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell --- .../chips/p9/procedures/hwp/memory/lib/ccs/ccs.C | 14 +-- .../chips/p9/procedures/hwp/memory/lib/ccs/ccs.H | 8 +- .../chips/p9/procedures/hwp/memory/lib/dimm/rank.C | 8 +- .../chips/p9/procedures/hwp/memory/lib/mss.H | 2 + .../p9/procedures/hwp/memory/lib/phy/ddr_phy.C | 38 +++---- .../p9/procedures/hwp/memory/lib/phy/ddr_phy.H | 36 +++---- .../chips/p9/procedures/hwp/memory/lib/phy/dp16.C | 17 ++-- .../chips/p9/procedures/hwp/memory/lib/port/port.H | 24 ++--- .../hwp/memory/lib/termination/slew_cal.C | 12 +-- .../p9/procedures/hwp/memory/lib/utils/poll.H | 5 +- .../p9/procedures/hwp/memory/lib/utils/scom.H | 110 +++++++++++++++++++++ 11 files changed, 194 insertions(+), 80 deletions(-) create mode 100644 src/import/chips/p9/procedures/hwp/memory/lib/utils/scom.H (limited to 'src/import/chips') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C index 5753fd577..c305a7f93 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C @@ -56,10 +56,10 @@ fapi2::ReturnCode start_stop( const fapi2::Target& i_target, fapi2::buffer l_buf; // Do we need to read this? We are setting the only bit defined in the scomdef? BRS - FAPI_TRY(fapi2::getScom(i_target, TT::CNTLQ_REG, l_buf)); + FAPI_TRY(mss::getScom(i_target, TT::CNTLQ_REG, l_buf)); - FAPI_TRY( fapi2::putScom(i_target, TT::CNTLQ_REG, - i_start_stop ? l_buf.setBit() : l_buf.setBit()) ); + FAPI_TRY( mss::putScom(i_target, TT::CNTLQ_REG, + i_start_stop ? l_buf.setBit() : l_buf.setBit()) ); fapi_try_exit: return fapi2::current_err; @@ -175,8 +175,8 @@ fapi2::ReturnCode execute( const fapi2::Target& i_target, // simple (straight line) CCS programs. Anything with a loop or such will need another mechanism. l_inst_iter->arr1.insertFromRight(l_inst_count + 1); - FAPI_TRY( fapi2::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0) ); - FAPI_TRY( fapi2::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1) ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0) ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1) ); // arr1 contains a specification of the delay and repeat after this instruction, as well // as a repeat. Total up the delays as we go so we know how long to wait before polling @@ -212,8 +212,8 @@ fapi2::ReturnCode execute( const fapi2::Target& i_target, // here as an instruction forces the CCS engine to wait the delay specified in // the last instruction in this array (which it otherwise doesn't do.) l_des.arr1.setBit(); - FAPI_TRY( fapi2::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0) ); - FAPI_TRY( fapi2::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1) ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0) ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1) ); FAPI_DBG("css inst %d fixup: 0x%016lX 0x%016lX (0x%lx, 0x%lx) %s", l_inst_count, l_des.arr0, l_des.arr1, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H index d5008f660..315d0a772 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H @@ -461,9 +461,9 @@ inline fapi2::ReturnCode select_ports( const fapi2::Target& i_target, uint64_ // Not handling multiple ports here, can't do that for CCS. BRS FAPI_TRY( l_ports.setBit(i_ports) ); - FAPI_TRY( fapi2::getScom(i_target, TT::MCB_CNTL_REG, l_data) ); + FAPI_TRY( mss::getScom(i_target, TT::MCB_CNTL_REG, l_data) ); l_data.insert(l_ports); - FAPI_TRY( fapi2::putScom(i_target, TT::MCB_CNTL_REG, l_data) ); + FAPI_TRY( mss::putScom(i_target, TT::MCB_CNTL_REG, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -563,7 +563,7 @@ template< fapi2::TargetType T, typename TT = ccsTraits > inline fapi2::ReturnCode read_mode( const fapi2::Target& i_target, fapi2::buffer& i_buffer) { FAPI_DBG("read mode 0x%llx", TT::MODEQ_REG); - return fapi2::getScom(i_target, TT::MODEQ_REG, i_buffer); + return mss::getScom(i_target, TT::MODEQ_REG, i_buffer); } /// @@ -577,7 +577,7 @@ inline fapi2::ReturnCode read_mode( const fapi2::Target& i_target, fapi2::buf template< fapi2::TargetType T, typename TT = ccsTraits > inline fapi2::ReturnCode write_mode( const fapi2::Target& i_target, const fapi2::buffer& i_buffer) { - return fapi2::putScom(i_target, TT::MODEQ_REG, i_buffer); + return mss::putScom(i_target, TT::MODEQ_REG, i_buffer); } /// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C index 8a618b813..c764f98fd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C @@ -265,9 +265,9 @@ fapi2::ReturnCode set_rank_pairs(const fapi2::Target& i_target) FAPI_DBG("setting rank pairs for %s. [%d,%d] (0x%08llx, 0x%08llx) csid: 0x%016llx", mss::c_str(i_target), l_rank_count[1], l_rank_count[0], l_rp0_register, l_rp1_register, l_csid_data); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_rp0_register) ); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_rp1_register) ); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_CSID_CFG_P0, l_csid_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_rp0_register) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_rp1_register) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_CSID_CFG_P0, l_csid_data) ); // HACK HACK HACK: put this in the code properly!! BRS { @@ -281,7 +281,7 @@ fapi2::ReturnCode set_rank_pairs(const fapi2::Target& i_target) l_fix_me.setBit(); l_fix_me.setBit(); FAPI_DBG("pc_rank_group: 0x%016llx", uint64_t(l_fix_me)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_RANK_GROUP_P0, l_fix_me) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_RANK_GROUP_P0, l_fix_me) ); } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss.H index 5ec6f752e..0cfa7bcd3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss.H @@ -31,6 +31,8 @@ #define _MSS_H_ #include +#include "utils/scom.H" + #include #include diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index cccb0b3e1..b8a9917cf 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -67,7 +67,7 @@ fapi2::ReturnCode scom_blastah( const fapi2::Target& i_target, const std::vec for (auto a : i_addrs) { - FAPI_TRY( fapi2::putScom(i_target, a, i_data) ); + FAPI_TRY( mss::putScom(i_target, a, i_data) ); ++count; } @@ -93,7 +93,7 @@ fapi2::ReturnCode scom_blastah( const std::vector >& i_targets, for (auto t : i_targets) { - FAPI_TRY( fapi2::putScom(t, i_addr, i_data) ); + FAPI_TRY( mss::putScom(t, i_addr, i_data) ); ++count; } @@ -145,9 +145,9 @@ fapi2::ReturnCode change_resetn( const fapi2::Target& i_targ { FAPI_DBG("Change reset to %s PHY: %s", (i_state == HIGH ? "high" : "low"), mss::c_str(p)); - FAPI_TRY( fapi2::getScom(p, MCA_MBA_CAL0Q, l_data) ); + FAPI_TRY( mss::getScom(p, MCA_MBA_CAL0Q, l_data) ); i_state == HIGH ? l_data.setBit() : l_data.clearBit(); - FAPI_TRY( fapi2::putScom(p, MCA_MBA_CAL0Q, l_data) ); + FAPI_TRY( mss::putScom(p, MCA_MBA_CAL0Q, l_data) ); } fapi_try_exit: @@ -221,7 +221,7 @@ fapi2::ReturnCode change_force_mclk_low (const fapi2::Target()) { - FAPI_TRY(fapi2::getScom( p, MCA_MBA_FARB5Q, l_data)); + FAPI_TRY(mss::getScom( p, MCA_MBA_FARB5Q, l_data)); if (i_state == mss::HIGH) { @@ -232,7 +232,7 @@ fapi2::ReturnCode change_force_mclk_low (const fapi2::Target(); } - FAPI_TRY(fapi2::putScom( p, MCA_MBA_FARB5Q, l_data)); + FAPI_TRY(mss::putScom( p, MCA_MBA_FARB5Q, l_data)); } fapi_try_exit: @@ -399,7 +399,7 @@ fapi2::ReturnCode ddr_phy_flush( const fapi2::Target& i_targ for (auto p : l_ports) { - FAPI_TRY(fapi2::putScomUnderMask(p, MCA_DDRPHY_PC_POWERDOWN_1_P0, l_data, l_mask) ); + FAPI_TRY(mss::putScomUnderMask(p, MCA_DDRPHY_PC_POWERDOWN_1_P0, l_data, l_mask) ); } fapi2::delay(DELAY_100NS, cycles_to_simcycles(ns_to_cycles(i_target, 100))); @@ -408,7 +408,7 @@ fapi2::ReturnCode ddr_phy_flush( const fapi2::Target& i_targ for (auto p : l_ports) { - FAPI_TRY(fapi2::putScomUnderMask(p, MCA_DDRPHY_PC_POWERDOWN_1_P0, 0, l_mask) ); + FAPI_TRY(mss::putScomUnderMask(p, MCA_DDRPHY_PC_POWERDOWN_1_P0, 0, l_mask) ); } fapi_try_exit: @@ -435,7 +435,7 @@ static inline fapi2::ReturnCode phy_block_broadcast( const fapi2::Target().insertFromRight<18, 4>(i), i_data) ); + FAPI_TRY( mss::putScom(i_target, l_addr | fapi2::buffer().insertFromRight<18, 4>(i), i_data) ); } fapi_try_exit: @@ -540,25 +540,25 @@ fapi2::ReturnCode rank_pair_primary_to_dimm( switch(i_rp) { case 0: - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_data) ); l_data.extractToRight(l_rank); break; case 1: - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR0_P0, l_data) ); l_data.extractToRight(l_rank); break; case 2: - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_data) ); l_data.extractToRight(l_rank); break; case 3: - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_RANK_PAIR1_P0, l_data) ); l_data.extractToRight(l_rank); break; @@ -599,7 +599,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target l_failed_dimm; - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_APB_FIR_ERR1_P0, l_fir_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_APB_FIR_ERR1_P0, l_fir_data) ); FAPI_DBG("initial cal FIR: 0x%016llx", uint64_t(l_fir_data)); @@ -609,7 +609,7 @@ fapi2::ReturnCode process_initial_cal_errors( const fapi2::Target(l_errors); l_err_data.extractToRight fapi2::ReturnCode set_pc_config0(const fapi2::Target& i_target) { fapi2::buffer l_data; - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) ); // Note: This needs to get the DRAM gen from an attribute. - 0x1 is DDR4 Note for Nimbus PHY // this is ignored and hard-wired to DDR4, per John Bialas 10/15 BRS @@ -771,7 +771,7 @@ fapi2::ReturnCode set_pc_config0(const fapi2::Target& i_target) l_data.setBit(); FAPI_DBG("phy pc_config0 0x%0llx", l_data); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_CONFIG0_P0, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -820,7 +820,7 @@ fapi2::ReturnCode set_pc_config1(const fapi2::Target& i_target) l_gen_index = l_dram_gen[0] | l_dram_gen[1]; // FOR NIMBUS PHY (as the protocol choice above is) BRS - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) ); l_data.insertFromRight(memory_type[l_type_index][l_gen_index]); @@ -832,7 +832,7 @@ fapi2::ReturnCode set_pc_config1(const fapi2::Target& i_target) l_data.setBit(); FAPI_DBG("phy pc_config1 0x%0llx", l_data); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) ); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H index dd7ee3fa4..eff335982 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H @@ -35,7 +35,7 @@ // Helper macro to condense the checking for PLL lock #define CHECK_PLL( __target, __register, __buffer, __mask ) \ - FAPI_TRY(fapi2::getScom( __target, __register, __buffer)); \ + FAPI_TRY(mss::getScom( __target, __register, __buffer)); \ if ((__buffer & __mask) != __mask) \ { \ FAPI_INF("PLL 0x%lx failed to lock 0x%lx", __register, __buffer); \ @@ -331,7 +331,7 @@ inline fapi2::ReturnCode dump_cal_registers( const fapi2::Target l_data; - FAPI_TRY( fapi2::getScom(i_target, r.first, l_data) ); + FAPI_TRY( mss::getScom(i_target, r.first, l_data) ); FAPI_DBG("dump %s: 0x%llx 0x%llx", r.second, r.first, l_data); } @@ -401,7 +401,7 @@ inline fapi2::ReturnCode setup_cal_config( const fapi2::Target(); FAPI_DBG("wc_config0 0x%llx (tWLO_tWLOE: %d)", l_data, mss::twlo_twloe(i_target)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG0_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG0_P0, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -497,7 +497,7 @@ inline fapi2::ReturnCode reset_wc_config1( const fapi2::Target(WR_LVL_SMALL_STEP); l_data.insertFromRight(WR_LVL_PRE_DLY); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG1_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG1_P0, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -529,7 +529,7 @@ inline fapi2::ReturnCode reset_wc_config2( const fapi2::Target(WR_CNTR_FW_RD_WR); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -569,7 +569,7 @@ inline fapi2::ReturnCode reset_wc_config3( const fapi2::Target(CMD_DQ_OFF); } - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG3_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG3_P0, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -600,7 +600,7 @@ inline fapi2::ReturnCode reset_seq_config0( const fapi2::Target(l_odt_rd[0][1]); FAPI_DBG("odt_rd_config0: 0x%016llx", uint64_t(l_data)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG0_P0, l_data) ); } { @@ -663,7 +663,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target(l_odt_rd[0][3]); FAPI_DBG("odt_rd_config1: 0x%016llx", uint64_t(l_data)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG1_P0, l_data) ); } { @@ -677,7 +677,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target(l_odt_rd[1][1]); FAPI_DBG("odt_rd_config2: 0x%016llx", uint64_t(l_data)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG2_P0, l_data) ); } { @@ -691,7 +691,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target(l_odt_rd[1][3]); FAPI_DBG("odt_rd_config3: 0x%016llx", uint64_t(l_data)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_RD_CONFIG3_P0, l_data) ); } // @@ -708,7 +708,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target(l_odt_wr[0][1]); FAPI_DBG("odt_wr_config0: 0x%016llx", uint64_t(l_data)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG0_P0, l_data) ); } { @@ -722,7 +722,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target(l_odt_wr[0][3]); FAPI_DBG("odt_wr_config1: 0x%016llx", uint64_t(l_data)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG1_P0, l_data) ); } { @@ -736,7 +736,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target(l_odt_wr[1][1]); FAPI_DBG("odt_wr_config2: 0x%016llx", uint64_t(l_data)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG2_P0, l_data) ); } { @@ -750,7 +750,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target(l_odt_wr[1][3]); FAPI_DBG("odt_wr_config3: 0x%016llx", uint64_t(l_data)); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_ODT_WR_CONFIG3_P0, l_data) ); } fapi_try_exit: @@ -786,8 +786,8 @@ inline fapi2::ReturnCode reset_seq_rd_wr_data( const fapi2::Target(MPR_PATTERN); FAPI_DBG("seq_rd_wr 0x%llx", l_data); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA0_P0, l_data) ); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA1_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA0_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_SEQ_RD_WR_DATA1_P0, l_data) ); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 81e50fc8c..8f171e7ff 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -31,6 +31,7 @@ #include #include +#include "../utils/scom.H" #include "dp16.H" #include @@ -163,7 +164,7 @@ fapi2::ReturnCode write_data_bit_enable( const fapi2::Target& i { // This is probably important enough to be seen all the time, not just debug FAPI_INF( "Setting up DATA_BIT_ENABLE 0x%llx (0x%llx) %s", rdp.first, rdp.second, mss::c_str(i_target) ); - FAPI_TRY( fapi2::putScom(i_target, rdp.first, rdp.second) ); + FAPI_TRY( mss::putScom(i_target, rdp.first, rdp.second) ); } fapi_try_exit: @@ -196,7 +197,7 @@ fapi2::ReturnCode read_clock_enable( const fapi2::Target& i_tar l_data.insertFromRight(rdp.second); FAPI_INF( "Setting up RDCLK RP%d 0x%llx (0x%llx) %s", rp, l_address, l_data, mss::c_str(i_target) ); - FAPI_TRY( fapi2::putScom(i_target, l_address, l_data) ); + FAPI_TRY( mss::putScom(i_target, l_address, l_data) ); } } @@ -230,7 +231,7 @@ fapi2::ReturnCode write_clock_enable( const fapi2::Target& i_ta l_data.insertFromRight(rdp.second); FAPI_INF( "Setting up WRCLK RP%d 0x%llx (0x%llx) %s", rp, l_address, l_data, mss::c_str(i_target) ); - FAPI_TRY( fapi2::putScom(i_target, l_address, l_data) ); + FAPI_TRY( mss::putScom(i_target, l_address, l_data) ); } } @@ -261,9 +262,9 @@ fapi2::ReturnCode reset_delay_values( const fapi2::Target& i_ta // Reset the write level values FAPI_INF( "Resetting write level values %s", mss::c_str(i_target) ); - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) ); l_data.setBit(); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_CONFIG2_P0, l_data) ); for (auto rp : l_rank_pairs) { @@ -274,7 +275,7 @@ fapi2::ReturnCode reset_delay_values( const fapi2::Target& i_ta l_address.insertFromRight<22, 2>(rp); FAPI_DBG( "Resetting DP16 gate delay 0x%llx %s", l_address, mss::c_str(i_target) ); - FAPI_TRY( fapi2::putScom(i_target, l_address, 0) ); + FAPI_TRY( mss::putScom(i_target, l_address, 0) ); } } @@ -316,8 +317,8 @@ fapi2::ReturnCode setup_sysclk( const fapi2::Target& i_targe for (auto a : l_addrs) { - FAPI_TRY( fapi2::putScom(p, a.first, l_data) ); - FAPI_TRY( fapi2::putScom(p, a.second, l_data) ); + FAPI_TRY( mss::putScom(p, a.first, l_data) ); + FAPI_TRY( mss::putScom(p, a.second, l_data) ); } } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H index 4b3f6637b..968c4d847 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/port/port.H @@ -102,9 +102,9 @@ fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target& i_target, states fapi2::buffer l_data; FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( fapi2::getScom(i_target, TT::FARB5Q_REG, l_data) ); + FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) ); l_data.writeBit(i_state); - FAPI_TRY( fapi2::putScom(i_target, TT::FARB5Q_REG, l_data) ); + FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -122,9 +122,9 @@ fapi2::ReturnCode change_refresh_enable( const fapi2::Target& i_target, state fapi2::buffer l_data; FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( fapi2::getScom(i_target, TT::REFRESH_REG, l_data) ); + FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) ); l_data.writeBit(i_state); - FAPI_TRY( fapi2::putScom(i_target, TT::REFRESH_REG, l_data) ); + FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -154,7 +154,7 @@ fapi2::ReturnCode enable_read_ecc( const fapi2::Target& i_target ) FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target)); - FAPI_TRY( fapi2::getScom(i_target, TT::ECC_REG, l_data) ); + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); l_data.clearBit(); l_data.clearBit(); @@ -166,7 +166,7 @@ fapi2::ReturnCode enable_read_ecc( const fapi2::Target& i_target ) // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. - FAPI_TRY( fapi2::putScom(i_target, TT::ECC_REG, l_data) ); + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); fapi_try_exit: return fapi2::current_err; @@ -191,7 +191,7 @@ template< fapi2::TargetType T, typename TT = portTraits > inline fapi2::ReturnCode draminit_entry_invariant( const fapi2::Target& i_target ) { fapi2::buffer l_data; - FAPI_TRY( fapi2::getScom(i_target, TT::FARB5Q_REG, l_data) ); + FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) ); if ((l_data.getBit() != HIGH) || (l_data.getBit() != LOW)) { @@ -199,7 +199,7 @@ inline fapi2::ReturnCode draminit_entry_invariant( const fapi2::Target& i_tar FAPI_INF("FARB5Q: 0x%llx, setting MUX_SEL, clearing RESET_ENABLE", uint64_t(l_data)); l_data.setBit(); l_data.clearBit(); - FAPI_TRY( fapi2::putScom(i_target, TT::FARB5Q_REG, l_data) ); + FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) ); } fapi_try_exit: @@ -220,12 +220,12 @@ fapi2::ReturnCode drive_mem_clks( const fapi2::Target& i_target, uint64_t i_p fapi2::buffer l_data; FAPI_DBG("Drive mem clocks"); - FAPI_TRY( fapi2::getScom(i_target, TT::FARB5Q_REG, l_data) ); + FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) ); l_data.insertFromRight(i_nclk); l_data.insertFromRight(i_pclk); - FAPI_TRY( fapi2::putScom(i_target, TT::FARB5Q_REG, l_data) ); + FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) ); return fapi2::FAPI2_RC_SUCCESS; @@ -245,13 +245,13 @@ template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode ddr_resetn( const fapi2::Target& i_target, bool i_state ) { fapi2::buffer l_data; - FAPI_TRY( fapi2::getScom(i_target, TT::FARB5Q_REG, l_data) ); + FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) ); if (l_data.getBit() != i_state) { l_data.writeBit(i_state); FAPI_DBG("ddr_resetn transitioning to %d (0x%llx)", i_state, l_data); - FAPI_TRY( fapi2::putScom(i_target, TT::FARB5Q_REG, l_data) ); + FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) ); } return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal.C b/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal.C index 906e8ced6..492184d52 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/termination/slew_cal.C @@ -195,7 +195,7 @@ fapi2::ReturnCode perform_slew_cal( MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_ADR0_TARGET_PR_OFFSET_LEN>(l_slew_rate.second); l_data.setBit(); - FAPI_TRY( fapi2::putScom(i_target, MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0, l_data) ); + FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0, l_data) ); mss::poll( i_target, MCA_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0, mss::poll_parameters(DELAY_100NS), [&](const size_t poll_remaining, const fapi2::buffer& stat_reg) -> bool @@ -212,7 +212,7 @@ fapi2::ReturnCode perform_slew_cal( FAPI_TRY( slew_cal_status(i_target, i_where_am_i, l_slew_rate.second, cal_status, status_register) ); // Get our calculated slew rate and process. - FAPI_TRY( fapi2::getScom(i_target, MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0, l_data) ); + FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0, l_data) ); l_data.extractToRight(calculated_slew); @@ -444,8 +444,8 @@ fapi2::ReturnCode slew_cal(const fapi2::Target& i_target) mss::pos(p), (ddr_type + 2), ddr_idx, ddr_freq, freq_idx, l_name); // Note: This is wrong. Cant' find the SLEW_CAL enable bit in n10_e9024, so leaving this here for now BRS - FAPI_TRY( fapi2::putScom(p, MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0, - fapi2::buffer().setBit()), + FAPI_TRY( mss::putScom(p, MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0, + fapi2::buffer().setBit()), "Error enabling slew calibration engine in DDRPHY_ADR_SLEW_CAL_CNTL register."); } } @@ -483,8 +483,8 @@ fapi2::ReturnCode slew_cal(const fapi2::Target& i_target) for (auto p : l_mcs_ports) { // Note: This is wrong. Cant' find the SLEW_CAL enable bit in n10_e9024, so leaving this here for now BRS - FAPI_TRY( fapi2::putScom(p, MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0, - fapi2::buffer().clearBit()), + FAPI_TRY( mss::putScom(p, MCA_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0, + fapi2::buffer().clearBit()), "Error disabling slew calibration engine in DDRPHY_ADR_SLEW_CAL_CNTL register."); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H index 4fc9dab60..462e251f4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/poll.H @@ -31,6 +31,7 @@ #define _MSS_POLL_H_ #include +#include "../utils/scom.H" #include "../shared/mss_const.H" #include "conversions.H" @@ -110,7 +111,7 @@ inline bool poll(const fapi2::Target& i_target, const uint64_t i_addr, for ( size_t l_poll_limit = i_params.iv_poll_count; l_poll_limit > 0; --l_poll_limit ) { - FAPI_TRY( fapi2::getScom(i_target, i_addr, l_reg) ); + FAPI_TRY( mss::getScom(i_target, i_addr, l_reg) ); if (i_fn(l_poll_limit, l_reg) == true) { @@ -126,7 +127,7 @@ inline bool poll(const fapi2::Target& i_target, const uint64_t i_addr, return false; fapi_try_exit: - FAPI_ERR("mss::poll() hit an error in fapi2::delay or fapi2::getScom"); + FAPI_ERR("mss::poll() hit an error in fapi2::delay or mss::getScom"); return false; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/scom.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/scom.H new file mode 100644 index 000000000..43ee2d5d7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/scom.H @@ -0,0 +1,110 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: chips/p9/procedures/hwp/memory/lib/utils/scom.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* EKB Project */ +/* */ +/* COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file scom.H +/// @brief Tools related to scom operations +/// +// *HWP HWP Owner: Brian Silver +// *HWP HWP Backup: Craig Hamilton +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_SCOM_H_ +#define _MSS_SCOM_H_ + +#include + +// +// Wrapping scom operations: We wrap fapi2::get/putScom for two reasons. The +// first is so that we can hook in to the base scom operations in the lab. This +// is expected to be used for test tracking and data gathering. The other +// reason is to facilitate sharing code with Z in the event they don't leverage +// fapi2. This gives us a place to define a common "hw access" API allowing +// P and Z to implement the underlying firmware API using different mechanisms. +// + +namespace mss +{ +/// @brief Reads a SCOM register from a chip. +/// @tparam K template parameter, passed in target. +/// @param[in] i_target HW target to operate on. +/// @param[in] i_address SCOM register address to read from. +/// @param[out] o_data Buffer that holds data read from HW target. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// @note We wrap scom operations in the mss library so that we can hook +/// into them in the lab. For IPL firmware, this should compile out. +template< fapi2::TargetType K > +inline fapi2::ReturnCode getScom(const fapi2::Target& i_target, const uint64_t i_address, + fapi2::buffer& o_data) +{ +#ifdef PSYSTEMS_MSS_LAB_ONLY + // Place holder for lab-hooks + return fapi2::getScom(i_target, i_address, o_data); +#else + return fapi2::getScom(i_target, i_address, o_data); +#endif +} + +/// @brief Writes a SCOM register on a chip. +/// @tparam K template parameter, passed in target. +/// @param[in] i_target HW target to operate on. +/// @param[in] i_address SCOM register address to write to. +/// @param[in] i_data Buffer that holds data to write into address. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// @note We wrap scom operations in the mss library so that we can hook +/// into them in the lab. For IPL firmware, this should compile out. +template< fapi2::TargetType K > +inline fapi2::ReturnCode putScom(const fapi2::Target& i_target, const uint64_t i_address, + const fapi2::buffer i_data) +{ +#ifdef PSYSTEMS_MSS_LAB_ONLY + // Place holder for lab-hooks + return fapi2::putScom(i_target, i_address, i_data); +#else + return fapi2::putScom(i_target, i_address, i_data); +#endif +} + +/// @brief Writes a SCOM register under mask on a chip +/// @tparam K template parameter, passed in target. +/// @param[in] i_target HW target to operate on. +/// @param[in] i_address SCOM register address to write to. +/// @param[in] i_data Buffer that holds data to write into address. +/// @param[in] i_mask Buffer that holds the mask value. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// @note We wrap scom operations in the mss library so that we can hook +/// into them in the lab. For IPL firmware, this should compile out. +template< fapi2::TargetType K > +inline fapi2::ReturnCode putScomUnderMask(const fapi2::Target& i_target, + const uint64_t i_address, + const fapi2::buffer i_data, + const fapi2::buffer i_mask) +{ +#ifdef PSYSTEMS_MSS_LAB_ONLY + // Place holder for lab-hooks + return fapi2::putScomUnderMask(i_target, i_address, i_data, i_mask); +#else + return fapi2::putScomUnderMask(i_target, i_address, i_data, i_mask); +#endif +} + +} +#endif -- cgit v1.2.1