From 2d0ea43ba4c6e0baf327b27aa7c8f1ae2e4a7f3c Mon Sep 17 00:00:00 2001 From: Shelton Leung Date: Fri, 28 Apr 2017 17:24:49 -0500 Subject: performance settings for best dd1 bw and latency, some risk level 100 Change-Id: Icc69ea7066a27e5de25b854b1e98c0c87912b60e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39830 Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Reviewed-by: Michael D. Pardeik Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39844 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- src/import/chips/p9/initfiles/p9.mca.scom.initfile | 178 +++++++++++++++++++- .../p9/procedures/hwp/initfiles/p9_mca_scom.C | 185 +++++++++++++++++---- 2 files changed, 319 insertions(+), 44 deletions(-) (limited to 'src/import/chips') diff --git a/src/import/chips/p9/initfiles/p9.mca.scom.initfile b/src/import/chips/p9/initfiles/p9.mca.scom.initfile index 87fbf52e7..f116a11cd 100644 --- a/src/import/chips/p9/initfiles/p9.mca.scom.initfile +++ b/src/import/chips/p9/initfiles/p9.mca.scom.initfile @@ -289,18 +289,19 @@ ispy MCP.PORT0.SRQ.MBA_DSM0Q_CFG_RDTAG_DLY [when=S] { # ATTR_EFF_DIMM_T # rdtag_dly > PHY DELAY + CL - 3 - rdptrdly # PHY DELAY = 12 for 1866 and 2133, 13 for 2400 and 2666, +1 for LRDIMM # rdptrdly = 1 + # 4/20/2017 during performance test, experimentally found can run at -1 value 17, def_IS_SIM; - 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM - 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM - 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM - 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM + 7 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM + 7 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM + 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM + 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==1) && def_IS_HW; # RDIMM - 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM - 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM - 10 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM - 10 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM + 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_1866==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM + 8 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2133==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM + 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2400==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM + 9 + MCS.ATTR_EFF_DRAM_CL[def_PORT_INDEX], (def_MSS_FREQ_EQ_2666==1) && (MCS.ATTR_EFF_DIMM_TYPE[def_PORT_INDEX][0]==3) && def_IS_HW; # LRDIMM } @@ -668,6 +669,17 @@ ispy MCP.PORT0.SRQ.MBA_FARB0Q_CFG_2N_ADDR [when=S] { 0b0, (SYS.ATTR_MSS_MRW_DRAM_2N_MODE==0x00) && (MCS.ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET==0x01); # use auto vpd val -> auto vpd val = 1n } +ispy MCP.PORT0.SRQ.MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING [when=S] { + spyv; + 0b1000; +} + +ispy MCP.PORT0.SRQ.MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING [when=S] { + spyv; + 0b1000; +} + + # Epsilon Settings per Power Bus Spreadsheet ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_JITTER_EPSILON [when=S] { @@ -706,6 +718,156 @@ ispy MC01.PORT0.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON [when=S] { } +################## +# ASYNC SETTINGS +################## + +define def_perf_tune_case = (MCBIST.ATTR_MSS_FREQ==2400) && (SYS.ATTR_FREQ_PB_MHZ==2000) && (SYS.ATTR_RISK_LEVEL>0); + + +# DD1 + +# "L" field +ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] { + spyv, expr; + 3, (def_perf_tune_case==0); # untuned + 5, (def_perf_tune_case==1); # tuned +} + +# "D" field +ispy MCP.PORT0.ECC64.SCOM.MBSECCQ_NEST_VAL_TO_DATA_DELAY [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] { + spyv, expr; + 0, (def_perf_tune_case==0); # untuned + 1, (def_perf_tune_case==1); # tuned +} + +# "dn" field +espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_NONBYPASS [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] { + spyv; + OFF; # untuned and tuned same value +} + +# "h" field +espy MCP.PORT0.ECC64.SCOM.MBSECCQ_DELAY_VALID_1X [when=S && ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES] { + spyv; + OFF; # untuned and tuned same value +} +############################ +# DD2 REFRESH BLOCK SETTINGS +############################ +# OVERVIEW +# Intention is to keep queues from filling up with commands that we +# wouldn't be able to service anyway due because they are being refreshed +# and starving out commands to another rank not being refreshed that could +# have been executed. +# If a portion of the command address matches the address range being +# refreshed, then the command will be blocked from getting into the queue. +# A hash of three rank bits are used to do the address matching and +# blocking. Which 3 rank bits are used for hash is configureable. +# RULES FOR BEST USE/PERFORMANCE +# 1) Refresh block should not be enabled if only 1 rank. No benefit in +# blocking traffic to save room for another rank if there is no other +# rank. +# 2) Not worth it to choose a mode that will block extra ranks than the +# rank being refreshed. Obvious case is if more than 8 ranks exist +# because by matching on just 3 bits, you'll inevitably block +# additional unnecessary ranks. Essentially all existing rank bits +# must be covered by 3 bit hash. If bits exist that can't all be +# covered by hash, then not worth enabling feature. +# DIALS +# (Enable bits) MCPERF2_ENABLE_REFRESH_BLOCK_SQ, MCPERF2_ENABLE_REFRESH_BLOCK_NSQ +# If enabled, commands will be blocked from getting into queues if their address bits +# (Mode select) MCPERF2_REFRESH_BLOCK_CONFIG +# CONFIG | HASH BITS | DESCRIPTION +# (0) 000 | s0, s1, s2 | Single slot, 1 mrank up to 8-high stack +# (1) 001 | m2, s1, s2 | Single-slot, 2 mrank, up to 4-high stack +# (2) 010 | d, s1, s2 | Dual-slot, 1 mrank/slot, up to 4-high stack +# (3) 011 | d, m2, s2 | Dual-slot, 2 mrank/slot, up to 2-high stack +# (4) 100 | d, m1, m2 | Dual-slot, 4 mrank/slot +# This field is DON'T CARE if not enabled (helps for simlplification) +# TABLE FOR IDEAL CONFIGS +# # of # of # of | # of | CONFIGS | SIMPLIFIED | +# d-bits m-bits s-bits | ranks | ALLOWED | CONFIG | NOTES +# ------------------------------------------------------------------- +# 0 0 0 | 1 | DISABLE | 0 | 1 rank only +# 0 0 1 | 2 | 0,1,2,3 | 0 | +# 0 0 2 | 4 | 0,1,2 | 0 | +# 0 0 3 | 8 | 0 | 0 | +# 0 1 0 | 2 | 1,3,4 | 1 | +# 0 1 1 | 4 | 1 | 1 | +# 0 1 2 | 8 | 1 | 1 | +# 0 1 3 | 16 | DISABLE | 1 | >8 ranks +# 0 2 0 | 4 | 4 | 4 | +# 0 2 1 | 8 | DISABLE | 4 | no exact match +# 0 2 2 | 16 | DISABLE | 4 | >8 ranks +# 0 2 3 | 32 | DISABLE | 4 | >8 ranks +# 1 0 0 | 2 | 2,3,4 | 2 | +# 1 0 1 | 4 | 2,3 | 2 | +# 1 0 2 | 8 | 2 | 2 | +# 1 0 3 | 16 | DISABLE | 2 | >8 ranks +# 1 1 0 | 4 | 3,4 | 3 | +# 1 1 1 | 8 | 3 | 3 | +# 1 1 2 | 16 | DISABLE | 3 | >8 ranks +# 1 1 3 | 32 | DISABLE | 3 | >8 ranks +# 1 2 0 | 8 | 4 | 4 | +# 1 2 1 | 16 | DISABLE | 4 | >8 ranks +# 1 2 2 | 32 | DISABLE | 4 | >8 ranks +# 1 2 3 | 64 | DISABLE | 4 | >8 ranks +# SIMPLIFIED CONFIGS +# CHOOSING TO ENABLE +# ENABLE | CONDITION +# OFF | if total number of ranks = 1 +# OFF | if total number of ranks > 8 +# OFF | if it's the one 8 rank case that doesn't match exact +# | (0 d-bits, 2 m-bits, 1 s-bit) +# ON | Else +# CHOOSING CONFIG VALUE +# # of # of | SIMPLIFIED +# d-bits m-bits | CONFIG +# ---------------------------- +# 0 0 | 0 +# 0 1 | 1 +# 0 2 | 4 +# 1 0 | 2 +# 1 1 | 3 +# 1 2 | 4 + +# def_NUM_RANKS + +define def_is_dual_slot = (MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][0]>0) + && (MCS.ATTR_EFF_NUM_RANKS_PER_DIMM[def_PORT_INDEX][1]>0); + +# Variable to indicate special 8 rank case we want refresh block disabled +# Note: 4 master ranks == 2 m-bits; height of 2 == 2 slave ranks == 1 s-bit +define def_refblock_off_special_case = (def_is_dual_slot==0) && (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0]==4) && (def_SLOT0_DRAM_STACK_HEIGHT==2); + +espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_ENABLE_REFRESH_BLOCK_SQ [when=S] { + spyv, expr; + OFF, (def_NUM_RANKS==1); + OFF, (def_NUM_RANKS>8); + OFF, (def_refblock_off_special_case==1); + ON, (def_NUM_RANKS>1) && (def_NUM_RANKS<=8) && (def_refblock_off_special_case==0); +} + +espy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_ENABLE_REFRESH_BLOCK_NSQ [when=S] { + spyv, expr; + OFF, (def_NUM_RANKS==1); + OFF, (def_NUM_RANKS>8); + OFF, (def_refblock_off_special_case==1); + ON, (def_NUM_RANKS>1) && (def_NUM_RANKS<=8) && (def_refblock_off_special_case==0); +} + + +ispy MC01.PORT0.ATCL.CL.CLSCOM.MCPERF2_REFRESH_BLOCK_CONFIG [when=S] { + spyv, expr; + 0b000, (def_is_dual_slot==0) && (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0]==1); # 0 d-bit, 0-m-bits + 0b001, (def_is_dual_slot==0) && (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0]==2); # 0 d-bit, 1-m-bits + 0b100, (def_is_dual_slot==0) && (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0]==4); # 0 d-bit, 2-m-bits + 0b010, (def_is_dual_slot==1) && (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0]==1); # 1 d-bit, 0-m-bits + 0b011, (def_is_dual_slot==1) && (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0]==2); # 1 d-bit, 1-m-bits + 0b100, (def_is_dual_slot==1) && (MCS.ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[def_PORT_INDEX][0]==4); # 1 d-bit, 2-m-bits +} + #################################################### # DD1 WORKAROUNDS #################################################### diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C index 2f3a6b890..bb90c5ee7 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_mca_scom.C @@ -29,50 +29,53 @@ using namespace fapi2; +constexpr uint64_t literal_1 = 1; +constexpr uint64_t literal_2 = 2; +constexpr uint64_t literal_0 = 0; +constexpr uint64_t literal_8 = 8; +constexpr uint64_t literal_0x0 = 0x0; +constexpr uint64_t literal_4 = 4; +constexpr uint64_t literal_0b000 = 0b000; +constexpr uint64_t literal_0b001 = 0b001; +constexpr uint64_t literal_0b100 = 0b100; +constexpr uint64_t literal_0b010 = 0b010; +constexpr uint64_t literal_0b011 = 0b011; constexpr uint64_t literal_0b0100 = 0b0100; constexpr uint64_t literal_0b11100 = 0b11100; constexpr uint64_t literal_0b110 = 0b110; constexpr uint64_t literal_0b0000000000000000000000000 = 0b0000000000000000000000000; constexpr uint64_t literal_0x1 = 0x1; -constexpr uint64_t literal_4 = 4; constexpr uint64_t literal_6 = 6; -constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_17 = 17; -constexpr uint64_t literal_0 = 0; -constexpr uint64_t literal_2 = 2; constexpr uint64_t literal_1867 = 1867; -constexpr uint64_t literal_8 = 8; +constexpr uint64_t literal_7 = 7; constexpr uint64_t literal_2134 = 2134; constexpr uint64_t literal_2401 = 2401; -constexpr uint64_t literal_9 = 9; constexpr uint64_t literal_2666 = 2666; constexpr uint64_t literal_3 = 3; -constexpr uint64_t literal_10 = 10; +constexpr uint64_t literal_9 = 9; constexpr uint64_t literal_24 = 24; constexpr uint64_t literal_5 = 5; constexpr uint64_t literal_267 = 267; constexpr uint64_t literal_1866 = 1866; +constexpr uint64_t literal_10 = 10; constexpr uint64_t literal_11 = 11; +constexpr uint64_t literal_0b1000 = 0b1000; constexpr uint64_t literal_0b011000 = 0b011000; constexpr uint64_t literal_0x02 = 0x02; constexpr uint64_t literal_0b1 = 0b1; constexpr uint64_t literal_0x01 = 0x01; constexpr uint64_t literal_0b0 = 0b0; constexpr uint64_t literal_0x00 = 0x00; -constexpr uint64_t literal_0b000 = 0b000; -constexpr uint64_t literal_0b100 = 0b100; -constexpr uint64_t literal_0b010 = 0b010; -constexpr uint64_t literal_0x0 = 0x0; -constexpr uint64_t literal_0b001 = 0b001; constexpr uint64_t literal_0b101 = 0b101; -constexpr uint64_t literal_0b011 = 0b011; constexpr uint64_t literal_0b111 = 0b111; -constexpr uint64_t literal_7 = 7; constexpr uint64_t literal_12 = 12; constexpr uint64_t literal_14 = 14; constexpr uint64_t literal_597 = 597; constexpr uint64_t literal_768 = 768; constexpr uint64_t literal_939 = 939; +constexpr uint64_t literal_2000 = 2000; +constexpr uint64_t literal_2400 = 2400; fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, const fapi2::Target& TGT1, const fapi2::Target& TGT2, @@ -83,6 +86,25 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, fapi2::ATTR_NAME_Type l_chip_id; FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT4, l_chip_id)); FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT4, l_chip_ec)); + fapi2::ATTR_EFF_NUM_RANKS_PER_DIMM_Type l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_NUM_RANKS_PER_DIMM, TGT2, l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM)); + fapi2::ATTR_CHIP_UNIT_POS_Type l_TGT0_ATTR_CHIP_UNIT_POS; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, TGT0, l_TGT0_ATTR_CHIP_UNIT_POS)); + uint64_t l_def_POSITION = l_TGT0_ATTR_CHIP_UNIT_POS; + uint64_t l_def_PORT_INDEX = (l_def_POSITION % literal_2); + uint64_t l_def_NUM_RANKS = (l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] + + l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_1]); + fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_Type l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, TGT2, l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM)); + uint64_t l_def_SLOT0_DENOMINATOR = ((l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == + literal_0x0) | l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0]); + uint64_t l_def_SLOT0_DRAM_STACK_HEIGHT = (l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] / + l_def_SLOT0_DENOMINATOR); + uint64_t l_def_is_dual_slot = ((l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] > literal_0) + && (l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_1] > literal_0)); + uint64_t l_def_refblock_off_special_case = (((l_def_is_dual_slot == literal_0) + && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_4)) + && (l_def_SLOT0_DRAM_STACK_HEIGHT == literal_2)); fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT3_ATTR_PROC_EPS_READ_CYCLES_T0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT3, l_TGT3_ATTR_PROC_EPS_READ_CYCLES_T0)); uint64_t l_def_MC_EPSILON_CFG_T0 = ((l_TGT3_ATTR_PROC_EPS_READ_CYCLES_T0 + literal_6) / literal_4); @@ -98,10 +120,6 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, uint64_t l_def_IS_HW = (l_TGT3_ATTR_IS_SIMULATION == literal_0); fapi2::ATTR_EFF_DIMM_TYPE_Type l_TGT2_ATTR_EFF_DIMM_TYPE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_TYPE, TGT2, l_TGT2_ATTR_EFF_DIMM_TYPE)); - fapi2::ATTR_CHIP_UNIT_POS_Type l_TGT0_ATTR_CHIP_UNIT_POS; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, TGT0, l_TGT0_ATTR_CHIP_UNIT_POS)); - uint64_t l_def_POSITION = l_TGT0_ATTR_CHIP_UNIT_POS; - uint64_t l_def_PORT_INDEX = (l_def_POSITION % literal_2); fapi2::ATTR_MSS_FREQ_Type l_TGT1_ATTR_MSS_FREQ; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_FREQ, TGT1, l_TGT1_ATTR_MSS_FREQ)); uint64_t l_def_MSS_FREQ_EQ_1866 = (l_TGT1_ATTR_MSS_FREQ < literal_1867); @@ -144,14 +162,6 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DRAM_2N_MODE, TGT3, l_TGT3_ATTR_MSS_MRW_DRAM_2N_MODE)); fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET_Type l_TGT2_ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, TGT2, l_TGT2_ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET)); - fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_Type l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, TGT2, l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM)); - uint64_t l_def_SLOT0_DENOMINATOR = ((l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == - literal_0x0) | l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0]); - fapi2::ATTR_EFF_NUM_RANKS_PER_DIMM_Type l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_NUM_RANKS_PER_DIMM, TGT2, l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM)); - uint64_t l_def_SLOT0_DRAM_STACK_HEIGHT = (l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] / - l_def_SLOT0_DENOMINATOR); uint64_t l_def_SLOT1_DENOMINATOR = ((l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_1] == literal_0x0) | l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_1]); uint64_t l_def_SLOT1_DRAM_STACK_HEIGHT = (l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_1] / @@ -160,8 +170,6 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, TGT2, l_TGT2_ATTR_MSS_VPD_MT_ODT_RD)); fapi2::ATTR_MSS_VPD_MT_ODT_WR_Type l_TGT2_ATTR_MSS_VPD_MT_ODT_WR; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, TGT2, l_TGT2_ATTR_MSS_VPD_MT_ODT_WR)); - uint64_t l_def_NUM_RANKS = (l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] + - l_TGT2_ATTR_EFF_NUM_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_1]); fapi2::ATTR_EFF_DRAM_TREFI_Type l_TGT2_ATTR_EFF_DRAM_TREFI; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TREFI, TGT2, l_TGT2_ATTR_EFF_DRAM_TREFI)); uint64_t l_def_REFRESH_INTERVAL = (l_TGT2_ATTR_EFF_DRAM_TREFI[l_def_PORT_INDEX] / (literal_8 * l_def_NUM_RANKS)); @@ -169,10 +177,91 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TRFC, TGT2, l_TGT2_ATTR_EFF_DRAM_TRFC)); fapi2::ATTR_EFF_DRAM_TRFC_DLR_Type l_TGT2_ATTR_EFF_DRAM_TRFC_DLR; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_TRFC_DLR, TGT2, l_TGT2_ATTR_EFF_DRAM_TRFC_DLR)); + fapi2::ATTR_RISK_LEVEL_Type l_TGT3_ATTR_RISK_LEVEL; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_RISK_LEVEL, TGT3, l_TGT3_ATTR_RISK_LEVEL)); + fapi2::ATTR_FREQ_PB_MHZ_Type l_TGT3_ATTR_FREQ_PB_MHZ; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, TGT3, l_TGT3_ATTR_FREQ_PB_MHZ)); + uint64_t l_def_perf_tune_case = (((l_TGT1_ATTR_MSS_FREQ == literal_2400) && (l_TGT3_ATTR_FREQ_PB_MHZ == literal_2000)) + && (l_TGT3_ATTR_RISK_LEVEL > literal_0)); fapi2::buffer l_scom_buffer; { FAPI_TRY(fapi2::getScom( TGT0, 0x5010824ull, l_scom_buffer )); + if ((l_def_NUM_RANKS == literal_1)) + { + constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_SQ_OFF = 0x0; + l_scom_buffer.insert<16, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_SQ_OFF ); + } + else if ((l_def_NUM_RANKS > literal_8)) + { + constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_SQ_OFF = 0x0; + l_scom_buffer.insert<16, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_SQ_OFF ); + } + else if ((l_def_refblock_off_special_case == literal_1)) + { + constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_SQ_OFF = 0x0; + l_scom_buffer.insert<16, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_SQ_OFF ); + } + else if ((((l_def_NUM_RANKS > literal_1) && (l_def_NUM_RANKS <= literal_8)) + && (l_def_refblock_off_special_case == literal_0))) + { + constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_SQ_ON = 0x1; + l_scom_buffer.insert<16, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_SQ_ON ); + } + + if ((l_def_NUM_RANKS == literal_1)) + { + constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ_OFF = 0x0; + l_scom_buffer.insert<17, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ_OFF ); + } + else if ((l_def_NUM_RANKS > literal_8)) + { + constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ_OFF = 0x0; + l_scom_buffer.insert<17, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ_OFF ); + } + else if ((l_def_refblock_off_special_case == literal_1)) + { + constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ_OFF = 0x0; + l_scom_buffer.insert<17, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ_OFF ); + } + else if ((((l_def_NUM_RANKS > literal_1) && (l_def_NUM_RANKS <= literal_8)) + && (l_def_refblock_off_special_case == literal_0))) + { + constexpr auto l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ_ON = 0x1; + l_scom_buffer.insert<17, 1, 63, uint64_t>(l_MC01_PORT0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_NSQ_ON ); + } + + if (((l_def_is_dual_slot == literal_0) + && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_1))) + { + l_scom_buffer.insert<13, 3, 61, uint64_t>(literal_0b000 ); + } + else if (((l_def_is_dual_slot == literal_0) + && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_2))) + { + l_scom_buffer.insert<13, 3, 61, uint64_t>(literal_0b001 ); + } + else if (((l_def_is_dual_slot == literal_0) + && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_4))) + { + l_scom_buffer.insert<13, 3, 61, uint64_t>(literal_0b100 ); + } + else if (((l_def_is_dual_slot == literal_1) + && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_1))) + { + l_scom_buffer.insert<13, 3, 61, uint64_t>(literal_0b010 ); + } + else if (((l_def_is_dual_slot == literal_1) + && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_2))) + { + l_scom_buffer.insert<13, 3, 61, uint64_t>(literal_0b011 ); + } + else if (((l_def_is_dual_slot == literal_1) + && (l_TGT2_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[l_def_PORT_INDEX][literal_0] == literal_4))) + { + l_scom_buffer.insert<13, 3, 61, uint64_t>(literal_0b100 ); + } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) { l_scom_buffer.insert<28, 4, 60, uint64_t>(literal_0b0100 ); @@ -212,42 +301,42 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, else if ((((l_def_MSS_FREQ_EQ_1866 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW)) { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_7 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } else if ((((l_def_MSS_FREQ_EQ_2133 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW)) { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_7 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } else if ((((l_def_MSS_FREQ_EQ_2400 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW)) { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } else if ((((l_def_MSS_FREQ_EQ_2666 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW)) { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } else if ((((l_def_MSS_FREQ_EQ_1866 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW)) { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } else if ((((l_def_MSS_FREQ_EQ_2133 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW)) { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } else if ((((l_def_MSS_FREQ_EQ_2400 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW)) { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_10 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } else if ((((l_def_MSS_FREQ_EQ_2666 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_3)) && l_def_IS_HW)) { - l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_10 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } if ((l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) @@ -334,12 +423,14 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, FAPI_TRY(fapi2::getScom( TGT0, 0x701090dull, l_scom_buffer )); l_scom_buffer.insert<5, 1, 63, uint64_t>(l_TGT1_ATTR_MSS_REORDER_QUEUE_SETTING ); + l_scom_buffer.insert<55, 4, 60, uint64_t>(literal_0b1000 ); FAPI_TRY(fapi2::putScom(TGT0, 0x701090dull, l_scom_buffer)); } { FAPI_TRY(fapi2::getScom( TGT0, 0x701090eull, l_scom_buffer )); l_scom_buffer.insert<6, 1, 63, uint64_t>(l_TGT1_ATTR_MSS_REORDER_QUEUE_SETTING ); + l_scom_buffer.insert<57, 4, 60, uint64_t>(literal_0b1000 ); if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) { @@ -727,6 +818,28 @@ fapi2::ReturnCode p9_mca_scom(const fapi2::Target& TGT0, { FAPI_TRY(fapi2::getScom( TGT0, 0x7010a0aull, l_scom_buffer )); + if ((l_def_perf_tune_case == literal_0)) + { + l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_3 ); + } + else if ((l_def_perf_tune_case == literal_1)) + { + l_scom_buffer.insert<16, 3, 61, uint64_t>(literal_5 ); + } + + if ((l_def_perf_tune_case == literal_0)) + { + l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_0 ); + } + else if ((l_def_perf_tune_case == literal_1)) + { + l_scom_buffer.insert<20, 2, 62, uint64_t>(literal_1 ); + } + + constexpr auto l_MCP_PORT0_ECC64_SCOM_MBSECCQ_DELAY_NONBYPASS_OFF = 0x0; + l_scom_buffer.insert<22, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_SCOM_MBSECCQ_DELAY_NONBYPASS_OFF ); + constexpr auto l_MCP_PORT0_ECC64_SCOM_MBSECCQ_DELAY_VALID_1X_OFF = 0x0; + l_scom_buffer.insert<19, 1, 63, uint64_t>(l_MCP_PORT0_ECC64_SCOM_MBSECCQ_DELAY_VALID_1X_OFF ); l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0b0 ); FAPI_TRY(fapi2::putScom(TGT0, 0x7010a0aull, l_scom_buffer)); } -- cgit v1.2.1