From ab3afc32f1e6d9577d42c8e93e3b517cc4d5b910 Mon Sep 17 00:00:00 2001 From: "Andre A. Marin" Date: Tue, 30 Apr 2019 18:24:49 -0500 Subject: Modify initial PRBS patter before DL link training starts This meant to help the Xilinx FPGA transceivers receive data more reliably. Since p9 used a PRBS setting of 250 ms, we are modifying the pre-IPL PRBS timer value from 0b100 to 0b101 (256 ms) to best match it. Change-Id: I9bb893061ef131e5b0831d36fcd1e36507c7eddd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76786 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Reviewed-by: Louis Stermole Reviewed-by: Mark Pizzutillo Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76876 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/import/chips/p9a/procedures') diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H index 1298699b5..7a11c0863 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H @@ -604,7 +604,7 @@ fapi2::ReturnCode setup_mc_config1_helper(const fapi2::Target& i_target) // CFG_DL0_CFG1_PREIPL_PRBS l_val.template insertFromRight(l_sim ? PREIPL_PRBS_1US : PREIPL_PRBS_64MS); + TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN>(l_sim ? PREIPL_PRBS_1US : PREIPL_PRBS_256MS); l_val.template writeBit(1); // Enable -- cgit v1.2.1