From 8f549e7548fb45819fc4fd8637448f428f14eec1 Mon Sep 17 00:00:00 2001 From: Mark Pizzutillo Date: Mon, 16 Sep 2019 17:08:27 -0400 Subject: Add code and workarounds for *_omi_setup and *_omi_train for Swift Change-Id: I139357a553e621b25b46bee6303357c712b67be2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83848 Tested-by: FSP CI Jenkins Dev-Ready: Steven B Janssen Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Christian R Geddes Reviewed-by: Louis Stermole Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83905 Reviewed-by: Daniel M Crowell Tested-by: Daniel M Crowell --- .../memory/lib/workarounds/p9a_omi_workarounds.C | 123 ++++++++++++++++----- .../memory/lib/workarounds/p9a_omi_workarounds.H | 52 ++++++++- 2 files changed, 142 insertions(+), 33 deletions(-) (limited to 'src/import/chips/p9a/procedures/hwp/memory/lib/workarounds') diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C index e4ac4af7c..783091c62 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C @@ -59,7 +59,7 @@ namespace mc /// @param[in] i_proc_type PROC type/name /// @return true/false perform workaround /// -bool is_prbs_omi_required_helper(const uint8_t i_ocmb_type, const uint8_t i_proc_type) +bool is_prbs_omi_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type) { // OMI Workaround Logic: // Explorer+Axone: OMI/PROC-side workaround off @@ -70,66 +70,91 @@ bool is_prbs_omi_required_helper(const uint8_t i_ocmb_type, const uint8_t i_proc } /// -/// @brief Determine whether to perform PRBS OMI workaround +/// @brief Helper function to determine whether PRBS axone OMI workarounds will be performed, that can be unit tested +/// +/// @param[in] i_ocmb_type OCMB type/name +/// @param[in] i_proc_type PROC type/name +/// @return true/false perform workaround +/// +bool is_prbs_omi_axone_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type) +{ + // OMI Workaround Logic: + // Explorer+Axone: Workaround on. + // Else: None + return ((i_proc_type == fapi2::ENUM_ATTR_NAME_AXONE) + && (i_ocmb_type == fapi2::ENUM_ATTR_NAME_EXPLORER)); // Explorer && axone +} + +/// +/// @brief Perform PRBS delay from prbs time and sim attributes +/// +/// @param[in] i_omi OMI target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode prbs_delay(const fapi2::Target& i_omi) +{ + uint8_t l_sim = 0; + uint32_t l_prbs_time = 0; + uint64_t l_prbs_time_scaled = 0; + + FAPI_TRY( mss::attr::get_is_simulation( l_sim) ); + + FAPI_TRY(mss::attr::get_omi_dl_preipl_prbs_time(i_omi, l_prbs_time), + "Error from FAPI_ATTR_GET (ATTR_OMI_DL_PREIPL_PRBS_TIME)"); + l_prbs_time_scaled = l_prbs_time * mss::common_timings::DELAY_1MS; + + FAPI_TRY(fapi2::delay(l_prbs_time_scaled, mss::common_timings::DELAY_1US)); + FAPI_DBG("OMI Training Pre-ipl PRBS Time = %dns", + (l_sim ? mss::common_timings::DELAY_1US : l_prbs_time_scaled)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Get PROC and OCMB types /// /// @param[in] i_ocmb_chip OCMB chip /// @param[in] i_proc_chip PROC chip /// @param[out] o_required workaround required /// @return FAPI2_RC_SUCCESS iff success /// -fapi2::ReturnCode is_prbs_omi_required( +fapi2::ReturnCode get_ocmb_proc_types( const fapi2::Target i_ocmb_chip, const fapi2::Target i_proc_chip, - bool& o_required) + uint8_t& o_ocmb_type, + uint8_t& o_proc_type) { - uint8_t l_ocmb_type = 0; - uint8_t l_proc_type = 0; - - FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_ocmb_chip, l_ocmb_type), + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_ocmb_chip, o_ocmb_type), "Error getting ATTR_NAME of %s", mss::c_str(i_ocmb_chip)); - FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_proc_chip, l_proc_type), + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_proc_chip, o_proc_type), "Error getting ATTR_NAME of %s", mss::c_str(i_proc_chip)); - o_required = is_prbs_omi_required_helper(l_ocmb_type, l_proc_type); - fapi_try_exit: return fapi2::current_err; } /// -/// @brief Perform the PRBS OMI workaround +/// @brief Perform the PRBS OMI workaround for gemini configurations /// /// @param[in] i_omi OMI /// @param[in] i_dl_x4_backoff_en backoff enable bit /// @return fapi2::FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode prbs_omi( +fapi2::ReturnCode omi_training_prbs_gem( const fapi2::Target i_omi, const uint8_t i_dl_x4_backoff_en) { FAPI_DBG("Performing PRBS OMI workaround on %s", mss::c_str(i_omi)); - uint32_t l_prbs_time = 0; - uint64_t l_prbs_time_scaled = 0; - uint8_t l_sim = 0; - FAPI_TRY(mss::attr::get_is_simulation(l_sim)); - - // Get PRBS time - FAPI_TRY(mss::attr::get_omi_dl_preipl_prbs_time(i_omi, l_prbs_time), - "Error from FAPI_ATTR_GET (ATTR_OMI_DL_PREIPL_PRBS_TIME)"); - l_prbs_time_scaled = l_prbs_time * mss::common_timings::DELAY_1MS; - // *_CONFIG0 should be the last one written, since it starts the training. // We are not using the pre-ipl PRBS auto training mode because it doesn't function properly in Axone // Enable training state 6 to send TS3 FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_TRAINING_STATE3, i_dl_x4_backoff_en)); - // Set configurable delay based on the PRBS ATTR and SIM mode - FAPI_TRY(fapi2::delay(l_prbs_time_scaled, mss::common_timings::DELAY_1US)); - FAPI_DBG("OMI Training Pre-ipl PRBS Time = %dns", - (l_sim ? mss::common_timings::DELAY_1US : l_prbs_time_scaled)); + FAPI_TRY(prbs_delay(i_omi)); // Enable training state 1 to send Pattern A FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_PATTERN_A, i_dl_x4_backoff_en)); @@ -138,6 +163,50 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Perform p9a_omi_train workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode omi_training_prbs( + const fapi2::Target i_omi, + const uint8_t i_dl_x4_backoff_en) +{ + FAPI_DBG("Performing OMI Train axone workaround on %s", mss::c_str(i_omi)); + + // Training mode 1: send Pattern A + FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_PATTERN_A, i_dl_x4_backoff_en)); + + FAPI_TRY(fapi2::delay(100 * mss::common_timings::DELAY_1MS, mss::common_timings::DELAY_1MS)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform p9a_omi_setup (pre-training) workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode pre_omi_training_prbs( + const fapi2::Target i_omi, + const uint8_t i_dl_x4_backoff_en) +{ + FAPI_DBG("Performing OMI Setup axone workaround on %s", mss::c_str(i_omi)); + + // Training mode 4: send State 1 + FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_TRAINING_STATE1, i_dl_x4_backoff_en)); + + FAPI_TRY(prbs_delay(i_omi)); + +fapi_try_exit: + return fapi2::current_err; +} + } // mc } // workarounds } // mss diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H index 45828a2af..4491a91e3 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H @@ -51,29 +51,69 @@ namespace mc /// @param[in] i_proc_type PROC type/name /// @return true/false perform workaround /// -bool is_prbs_omi_required_helper(const uint8_t i_ocmb_type, const uint8_t i_proc_type); +bool is_prbs_omi_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type); /// -/// @brief Determine whether to perform PRBS OMI workaround +/// @brief Helper function to determine whether PRBS axone OMI workarounds will be performed, that can be unit tested +/// +/// @param[in] i_ocmb_type OCMB type/name +/// @param[in] i_proc_type PROC type/name +/// @return true/false perform workaround +/// +bool is_prbs_omi_axone_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type); + +/// +/// @brief Perform PRBS delay from prbs time and sim attributes +/// +/// @param[in] i_omi OMI target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode prbs_delay(const fapi2::Target& i_omi); + +/// +/// @brief Get PROC and OCMB types /// /// @param[in] i_ocmb_chip OCMB chip /// @param[in] i_proc_chip PROC chip /// @param[out] o_required workaround required /// @return FAPI2_RC_SUCCESS iff success /// -fapi2::ReturnCode is_prbs_omi_required( +fapi2::ReturnCode get_ocmb_proc_types( const fapi2::Target i_ocmb_chip, const fapi2::Target i_proc_chip, - bool& o_required); + uint8_t& o_ocmb_type, + uint8_t& o_proc_type); /// -/// @brief Perform the PRBS OMI workaround +/// @brief Perform the PRBS OMI workaround for gemini configurations /// /// @param[in] i_omi OMI /// @param[in] i_dl_x4_backoff_en backoff enable bit /// @return fapi2::FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode prbs_omi( +fapi2::ReturnCode omi_training_prbs_gem( + const fapi2::Target i_omi, + const uint8_t i_dl_x4_backoff_en); + +/// +/// @brief Perform p9a_omi_train workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode omi_training_prbs( + const fapi2::Target i_omi, + const uint8_t i_dl_x4_backoff_en); + +/// +/// @brief Perform p9a_omi_setup (pre-training) workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode pre_omi_training_prbs( const fapi2::Target i_omi, const uint8_t i_dl_x4_backoff_en); -- cgit v1.2.1