From 8f549e7548fb45819fc4fd8637448f428f14eec1 Mon Sep 17 00:00:00 2001 From: Mark Pizzutillo Date: Mon, 16 Sep 2019 17:08:27 -0400 Subject: Add code and workarounds for *_omi_setup and *_omi_train for Swift Change-Id: I139357a553e621b25b46bee6303357c712b67be2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83848 Tested-by: FSP CI Jenkins Dev-Ready: Steven B Janssen Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Christian R Geddes Reviewed-by: Louis Stermole Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83905 Reviewed-by: Daniel M Crowell Tested-by: Daniel M Crowell --- src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/import/chips/p9a/procedures/hwp/memory/lib/mc') diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H index 5cf787640..48f5cb222 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H @@ -252,13 +252,13 @@ fapi2::ReturnCode setup_mc_config0( l_val.template insertFromRight( - mss::omi::phy_ctr_mode::PHY_CTR_MODE_50US); + mss::omi::phy_ctr_mode::PHY_CTR_MODE_60MS); // CFG_DL0_RUNLANE_OVRD_ENABLE: When enabled, the dl0 will drive run lane to the PHY for all training states. l_val.writeBit(0); // CFG_DL0_PWRMGT_ENABLE: dl0 power management enabled - l_val.writeBit(1); + l_val.writeBit(0); // CFG_DL0_QUARTER_WIDTH_BACKOFF_ENABLE: dl0 x1 backoff enabled l_val.writeBit(0); @@ -283,6 +283,9 @@ fapi2::ReturnCode setup_mc_config0( // CFG_DL0_RESET: dl0 reset - Reset dl0 back to traning state 0 l_val.writeBit(0); + FAPI_DBG("Writing 0x%16llx to MC_REG2_DL0_CONFIG0 (0x%16llx) of %s", + l_val, TT::MC_REG2_DL0_CONFIG0, mss::c_str(i_target)); + FAPI_TRY( mss::putScom(i_target, TT::MC_REG2_DL0_CONFIG0, l_val) ); fapi_try_exit: -- cgit v1.2.1