From 3c4217b17494a02bb2b6116e13797395e933f173 Mon Sep 17 00:00:00 2001 From: Adam Hale Date: Fri, 4 May 2018 09:55:11 -0500 Subject: Added RMW Thresh10 Spec Disable to initfiles Change-Id: Ie0e4939a1c1094122ebde4a25f4332bf20f5f356 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58362 Reviewed-by: SHELTON LEUNG Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Reviewed-by: DANIEL C. HOWE Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58367 Tested-by: Jenkins OP Build CI Reviewed-by: Daniel M. Crowell --- src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/import/chips/p9') diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C index a864533fb..38e94660b 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9c_dmi_scom.C @@ -35,6 +35,7 @@ constexpr uint64_t literal_12 = 12; constexpr uint64_t literal_4 = 4; constexpr uint64_t literal_0b0100 = 0b0100; constexpr uint64_t literal_28 = 28; +constexpr uint64_t literal_0b01010 = 0b01010; constexpr uint64_t literal_0 = 0; constexpr uint64_t literal_8 = 8; constexpr uint64_t literal_0x1 = 0x1; @@ -125,6 +126,7 @@ fapi2::ReturnCode p9c_dmi_scom(const fapi2::Target& TGT0 constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_DISP_OFF = 0x0; l_scom_buffer.insert<18, 1, 63, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ENABLE_REFRESH_BLOCK_DISP_OFF ); l_scom_buffer.insert<50, 5, 59, uint64_t>(literal_28 ); + l_scom_buffer.insert<55, 5, 59, uint64_t>(literal_0b01010 ); if ((l_def_ENABLE_DYNAMIC_64_128B_READS == literal_1)) { -- cgit v1.2.1