From 1f8764f7c1673eb85a40ab36be14888f84e57545 Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Mon, 19 Sep 2016 14:44:16 +0200 Subject: FFDC Updates Change-Id: I75faf871652e5320889961516b203ad5356c7843 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29885 Reviewed-by: Soma Bhanutej Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Deepak Kodihalli Tested-by: Hostboot CI Reviewed-by: Sachin Gupta Reviewed-by: PARVATHI RACHAKONDA Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29887 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../chips/p9/procedures/hwp/perv/p9_sbe_common.C | 21 +- .../xml/error_info/p9_sbe_common_errors.xml | 565 +++++++++++++++++++-- 2 files changed, 528 insertions(+), 58 deletions(-) (limited to 'src/import/chips/p9') diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C index c35740606..18315b0ec 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_common.C @@ -120,7 +120,11 @@ fapi2::ReturnCode p9_sbe_common_align_chiplets(const FAPI_DBG("Loop Count :%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::CPLT_NOT_ALIGNED_ERR(), + fapi2::CPLT_NOT_ALIGNED_ERR() + .set_TARGET_CHIPLET(i_target_chiplets) + .set_PERV_CPLT_STAT0(l_data64) + .set_LOOP_COUNT(l_timeout) + .set_HW_DELAY(NS_DELAY), "ERROR:CHIPLET NOT ALIGNED"); FAPI_DBG("For all chiplets: disable alignement"); @@ -185,6 +189,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_sl_clkregion_status == l_regions, fapi2::NEST_SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } @@ -198,6 +203,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_sl_clkregion_status == l_regions, fapi2::NEST_SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "Clock running for sl type not matching with expected values"); } @@ -221,6 +227,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_nsl_clkregion_status == l_regions, fapi2::NEST_NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } @@ -234,6 +241,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_nsl_clkregion_status == l_regions, fapi2::NEST_NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "Clock running for nsl type not matching with expected values"); } @@ -257,6 +265,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_ary_clkregion_status == l_regions, fapi2::NEST_ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } @@ -270,6 +279,7 @@ fapi2::ReturnCode p9_sbe_common_check_cc_status_function( FAPI_ASSERT(l_ary_clkregion_status == l_regions, fapi2::NEST_ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "Clock running for ary type not matching with expected values"); } @@ -429,7 +439,11 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_DBG("Loop Count after CPLT_OPCG_DONE_DC polling:%d", l_timeout); FAPI_ASSERT(l_timeout > 0, - fapi2::CPLT_OPCG_DONE_NOT_SET_ERR(), + fapi2::CPLT_OPCG_DONE_NOT_SET_ERR() + .set_TARGET_CHIPLET(i_target) + .set_PERV_CPLT_STAT0(l_data64) + .set_LOOP_COUNT(l_timeout) + .set_HW_DELAY(NS_DELAY), "ERROR:CHIPLET OPCG DONE NOT SET AFTER CLOCK START STOP CMD"); //To do do checking only for chiplets that dont have Master-slave mode enabled @@ -456,6 +470,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_sl_clock_status == l_exp_sl_clock_status, fapi2::SL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_SL(l_sl_clock_status), "CLOCK RUNNING STATUS FOR SL TYPE NOT MATCHING WITH EXPECTED VALUES"); @@ -468,6 +483,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_nsl_clock_status == l_exp_nsl_clock_status, fapi2::NSL_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_NSL(l_nsl_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR NSL TYPE"); @@ -480,6 +496,7 @@ fapi2::ReturnCode p9_sbe_common_clock_start_stop(const FAPI_ASSERT(l_ary_clock_status == l_exp_ary_clock_status, fapi2::ARY_ERR() + .set_TARGET_CHIPLET(i_target) .set_READ_CLK_ARY(l_ary_clock_status), "CLOCK RUNNING STATUS IS NOT MATCHING WITH EXPECTED VALUE FOR ARRAY TYPE"); } diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml index cdd42e6ee..6642ea002 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml @@ -25,61 +25,514 @@ - - - - - RC_ARY_ERR - ary_thold status not matching the expected value in clock start stop sequence - READ_CLK_ARY - - - - - RC_NSL_ERR - nsl_thold status not matching the expected value in clock start stop sequence - READ_CLK_NSL - - - - - RC_SL_ERR - sl_thold status not matching the expected value in clock start stop sequence - READ_CLK_SL - - - - - RC_CPLT_NOT_ALIGNED_ERR - Chiplet not aligned - - - - - RC_CPLT_OPCG_DONE_NOT_SET_ERR - Chiplet OPCG_DONE not set after clock start/stop command - - - - - RC_NEST_ARY_ERR - ary_thold status not matching the expected value in clock start stop sequence - READ_CLK_ARY - - - - - RC_NEST_NSL_ERR - nsl_thold status not matching the expected value in clock start stop sequence - READ_CLK_NSL - - - - - RC_NEST_SL_ERR - sl_thold status not matching the expected value in clock start stop sequence - READ_CLK_SL - - + + + ROOT_CTRL_REGISTERS_CFAM + PERV_ROOT_CTRL0_FSI + PERV_ROOT_CTRL1_FSI + PERV_ROOT_CTRL2_FSI + PERV_ROOT_CTRL3_FSI + PERV_ROOT_CTRL4_FSI + PERV_ROOT_CTRL5_FSI + PERV_ROOT_CTRL6_FSI + PERV_ROOT_CTRL7_FSI + PERV_ROOT_CTRL8_FSI + + + PERV_CTRL_REGISTERS_CFAM + PERV_PERV_CTRL0_FSI + PERV_PERV_CTRL1_FSI + + + FSI2PIB_STATUS + PERV_FSI2PIB_STATUS_FSI + + + OSC_SWITCH_SENSE_REGISTER_CFAM + PERV_SNS1LTH_FSI + + + OSC_SWITCH_SENSE_REGISTER + PERV_SNS1LTH_SCOM + + + OSC_ERROR_HOLD + PERV_TP_OSCERR_HOLD + + + ROOT_CTRL_REGISTERS + PERV_ROOT_CTRL0_SCOM + PERV_ROOT_CTRL1_SCOM + PERV_ROOT_CTRL2_SCOM + PERV_ROOT_CTRL3_SCOM + PERV_ROOT_CTRL4_SCOM + PERV_ROOT_CTRL5_SCOM + PERV_ROOT_CTRL6_SCOM + PERV_ROOT_CTRL7_SCOM + PERV_ROOT_CTRL8_SCOM + + + PERV_CTRL_REGISTERS + PERV_PERV_CTRL0_SCOM + PERV_PERV_CTRL1_SCOM + + + NET_CTRL_REGISTERS + PERV_NET_CTRL0 + PERV_NET_CTRL1 + + + CPLT_CTRL_REGISTERS + PERV_CPLT_CTRL0 + PERV_CPLT_CTRL1 + + + CPLT_CONFIG_REGISTERS + PERV_CPLT_CONF0 + PERV_CPLT_CONF1 + + + OTHER_CPLT_REGISTERS + PERV_CPLT_STAT0 + PERV_CPLT_MASK0 + + + PLL_LOCK_REG + PERV_PLL_LOCK_REG + + + I2C_REGISTERS + PU_CONTROL_REGISTER_B + PU_STATUS_REGISTER_B + PU_COMMAND_REGISTER_B + PU_MODE_REGISTER_B + PU_WATER_MARK_REGISTER_B + PU_INTERRUPT_MASK_REGISTER_READ_B + PU_INTERRUPT_COND_B + PU_INTERRUPTS_B + PU_STATUS_REGISTER_ENGINE_B + PU_EXTENDED_STATUS_B + PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B + PU_I2C_BUSY_REGISTER_B + + + OPCG_CTRL_REGISTERS + PERV_OPCG_ALIGN + PERV_OPCG_REG0 + PERV_OPCG_REG1 + PERV_OPCG_REG2 + + + CC_STATUS_REGISTERS + PERV_SCAN_REGION_TYPE + PERV_CLK_REGION + PERV_CLOCK_STAT_SL + PERV_CLOCK_STAT_NSL + PERV_CLOCK_STAT_ARY + PERV_BIST + + + ERROR_STATUS_OF_CC + PERV_ERROR_STATUS + + + CC_REGISTERS + PERV_XSTOP1 + PERV_XSTOP2 + PERV_XSTOP3 + PERV_OPCG_CAPT1 + PERV_OPCG_CAPT2 + PERV_OPCG_CAPT3 + PERV_DBG_CBS_CC + + + + + RC_ARY_ERR + ary_thold status not matching the expected value in clock start stop sequence + TARGET_CHIPLET + + NET_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CONFIG_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OTHER_CPLT_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OPCG_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_STATUS_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + ERROR_STATUS_OF_CC + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + READ_CLK_ARY + + + + + RC_NSL_ERR + nsl_thold status not matching the expected value in clock start stop sequence + TARGET_CHIPLET + + NET_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CONFIG_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OTHER_CPLT_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OPCG_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_STATUS_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + ERROR_STATUS_OF_CC + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + READ_CLK_NSL + + + + + RC_SL_ERR + sl_thold status not matching the expected value in clock start stop sequence + TARGET_CHIPLET + + NET_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CONFIG_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OTHER_CPLT_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OPCG_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_STATUS_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + ERROR_STATUS_OF_CC + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + READ_CLK_SL + + + + + RC_CPLT_NOT_ALIGNED_ERR + Chiplet not aligned + TARGET_CHIPLET + + NET_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CONFIG_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OTHER_CPLT_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OPCG_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_STATUS_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + ERROR_STATUS_OF_CC + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + PERV_CPLT_STAT0 + LOOP_COUNT + HW_DELAY + + + + + RC_CPLT_OPCG_DONE_NOT_SET_ERR + Chiplet OPCG_DONE not set after clock start/stop command + TARGET_CHIPLET + + NET_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CONFIG_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OTHER_CPLT_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OPCG_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_STATUS_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + ERROR_STATUS_OF_CC + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + PERV_CPLT_STAT0 + LOOP_COUNT + HW_DELAY + + + + + RC_NEST_ARY_ERR + ary_thold status not matching the expected value in clock start stop sequence + TARGET_CHIPLET + + NET_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CONFIG_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OTHER_CPLT_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OPCG_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_STATUS_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + ERROR_STATUS_OF_CC + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + READ_CLK_ARY + + + + + RC_NEST_NSL_ERR + nsl_thold status not matching the expected value in clock start stop sequence + TARGET_CHIPLET + + NET_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CONFIG_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OTHER_CPLT_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OPCG_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_STATUS_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + ERROR_STATUS_OF_CC + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + READ_CLK_NSL + + + + + RC_NEST_SL_ERR + sl_thold status not matching the expected value in clock start stop sequence + TARGET_CHIPLET + + NET_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CPLT_CONFIG_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OTHER_CPLT_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + OPCG_CTRL_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_STATUS_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + + ERROR_STATUS_OF_CC + TARGET_CHIPLET + TARGET_TYPE_PERV + + + CC_REGISTERS + TARGET_CHIPLET + TARGET_TYPE_PERV + + READ_CLK_SL + + -- cgit v1.2.1