From c9b82b3883b174d1cf181e9f0b9c9f261ccfa132 Mon Sep 17 00:00:00 2001 From: Alvin Wang Date: Tue, 29 Jan 2019 02:13:09 -0600 Subject: Adds exp_draminit_mc Change-Id: Ib4a31d2893c5524e3b2ce9128a2c4900bd82b2c0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68597 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Reviewed-by: Louis Stermole Tested-by: Hostboot CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68920 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell --- .../hwp/memory/lib/dimm/ddr4/nvdimm_utils.C | 4 +- .../procedures/hwp/memory/lib/fir/memdiags_fir.C | 4 +- .../chips/p9/procedures/hwp/memory/lib/mc/mc.C | 8 +- .../chips/p9/procedures/hwp/memory/lib/mc/port.C | 4 +- .../chips/p9/procedures/hwp/memory/lib/mc/port.H | 305 ++++----------------- .../hwp/memory/lib/mss_attribute_accessors.H | 67 +++-- .../procedures/hwp/memory/lib/shared/mss_const.H | 24 -- .../hwp/memory/lib/workarounds/mca_workarounds.C | 5 +- .../memory/lib/workarounds/mcbist_workarounds.C | 6 +- .../p9/procedures/hwp/memory/p9_mss_draminit.C | 5 +- .../p9/procedures/hwp/memory/p9_mss_draminit_mc.C | 13 +- .../hwp/memory/p9_mss_draminit_training.C | 4 +- .../xml/attribute_info/memory_mrw_attributes.xml | 17 +- 13 files changed, 135 insertions(+), 331 deletions(-) (limited to 'src/import/chips/p9/procedures') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C index 2c579a4ef..c69ae7656 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C @@ -268,13 +268,13 @@ fapi2::ReturnCode pda_vref_latch( const fapi2::Target& } // Disable refresh - FAPI_TRY( mss::change_refresh_enable(l_mca, states::LOW) ); + FAPI_TRY( mss::change_refresh_enable(l_mca, states::LOW) ); // execute_wr_vref_latch(l_container) FAPI_TRY( mss::ddr4::pda::execute_wr_vref_latch(l_container) ) // Enable refresh - FAPI_TRY( mss::change_refresh_enable(l_mca, states::HIGH) ); + FAPI_TRY( mss::change_refresh_enable(l_mca, states::HIGH) ); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C index 7aa41f6d4..31d9977b7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -130,7 +130,7 @@ fapi2::ReturnCode after_memdiags( const fapi2::Target& i_tar FAPI_TRY( mss::putScom(p, MCA_ACTION1, l_aue_buffer) ); // Note: We also want to include the following setup RCD recovery and port fail - FAPI_TRY( mss::change_port_fail_disable(p, mss::LOW) ); + FAPI_TRY( mss::change_port_fail_disable(p, mss::LOW) ); FAPI_TRY( mss::change_rcd_recovery_disable(p, mss::LOW) ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index 5d5db14ad..c56b1ff90 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -88,7 +88,8 @@ fapi2::ReturnCode set_pwr_cntrl_reg(const fapi2::Target& uint8_t l_pwr_cntrl = 0; fapi2::buffer l_data; - FAPI_TRY(mrw_power_control_requested(l_pwr_cntrl), "Error in set_pwr_cntrl_reg"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + l_pwr_cntrl), "Error in set_pwr_cntrl_reg"); FAPI_TRY(read_mbarpc0(i_target, l_data)); l_data.insertFromRight(MAXALL_MINALL); @@ -137,7 +138,8 @@ fapi2::ReturnCode set_str_reg(const fapi2::Target& i_tar uint8_t l_str_enable = 0; fapi2::buffer l_data; - FAPI_TRY(mrw_power_control_requested(l_str_enable), "Error in set_pwr_cntrl_reg"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + l_str_enable), "Error in set_pwr_cntrl_reg"); FAPI_TRY(read_mbastr0(i_target, l_data)); //Write bit if STR should be enabled diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index e527d37f5..0488fd579 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -72,7 +72,7 @@ constexpr uint64_t BIT_SPARE_7 = 15; // 7: SPARE template<> fapi2::ReturnCode enable_periodic_cal( const fapi2::Target& i_target ) { - typedef portTraits TT; + typedef portTraits TT; uint32_t l_memcal_interval = 0; uint32_t l_zqcal_interval = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 0a44ca640..1b66d66bf 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -25,7 +25,7 @@ /// /// @file port.H -/// @brief Code to support ports (phy _ mc for certain operations) +/// @brief Code to support ports /// // *HWP HWP Owner: Stephen Glancy // *HWP HWP Backup: Andre Marin @@ -38,35 +38,41 @@ #include +#include +#include +#include +#include #include #include -#include #include #include -#include #include -#include #include namespace mss { -// I have a dream that port code can be shared among controllers. So, I drive the -// engine from a set of traits. This might be folly. Allow me to dream. BRS - -template< fapi2::TargetType T > -class portTraits; - -// Centaur port traits +/// +/// @brief ATTR_MSS_MVPD_FWMS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint32_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Mark store records from MPVD Lx +/// keyword +/// template<> -class portTraits +inline fapi2::ReturnCode mvpd_fwms(const fapi2::Target& i_target, + uint32_t (&o_array)[mss::MARK_STORE_COUNT]) { - public: -}; + return mvpd_fwms(i_target, &o_array[0]); +} + + // Nimbus port traits template<> -class portTraits +class portTraits { public: static constexpr uint64_t FARB5Q_REG = MCA_MBA_FARB5Q; @@ -78,6 +84,7 @@ class portTraits static constexpr uint64_t CAL2Q_REG = MCA_MBA_CAL2Q; static constexpr uint64_t CAL3Q_REG = MCA_MBA_CAL3Q; static constexpr uint64_t DSM0Q_REG = MCA_MBA_DSM0Q; + static constexpr uint64_t FWMS_REG = MCA_FWMS0; // Danger Will Robinson MCA_DDRPHY_PC_PER_ZCAL_CONFIG_P0 uses PHY rank ordinal numbers // which are different between PHYs. So if you're playing with this register, be sure to map rank numbers. @@ -112,6 +119,9 @@ class portTraits CFG_DDR_RESETN = MCA_MBA_FARB5Q_CFG_DDR_RESETN, CFG_CCS_ADDR_MUX_SEL = MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL, + FWMS0_MARK = MCA_FWMS0_MARK, + FWMS0_EXIT_1 = MCA_FWMS0_EXIT_1, + REFRESH_ENABLE = MCA_MBAREF0Q_CFG_REFRESH_ENABLE, ECC_CHECK_DISABLE = MCA_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT, @@ -231,6 +241,8 @@ class portTraits RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY, + RECR_MBSECCQ_DATA_INVERSION = MCA_RECR_MBSECCQ_DATA_INVERSION, + RECR_MBSECCQ_DATA_INVERSION_LEN = MCA_RECR_MBSECCQ_DATA_INVERSION_LEN, RECR_READ_POINTER_DLY_LEN = MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN, DSM0Q_RDTAG_DLY = MCA_MBA_DSM0Q_CFG_RDTAG_DLY, DSM0Q_RDTAG_DLY_LEN = MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, @@ -271,43 +283,8 @@ class portTraits }; }; -/// -/// @brief Read the read ECC Control register -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[out] o_buffer the buffer to write the register data into -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode read_recr_register( const fapi2::Target& i_target, fapi2::buffer& o_buffer ) -{ - FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, o_buffer) ); - FAPI_INF( "Read ECC Control register is 0x%016lx for %s", uint64_t(o_buffer), mss::c_str(i_target) ); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write to RECR register -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_buffer the buffer that holds the register data to write -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode write_recr_register( const fapi2::Target& i_target, const fapi2::buffer& i_buffer ) -{ - FAPI_INF( "Change Read ECC Control register to 0x%016lx for %s", i_buffer, mss::c_str(i_target) ); - - FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, i_buffer) ); - -fapi_try_exit: - return fapi2::current_err; -} /// /// @brief Get the read pointer delay value from RECR @@ -316,7 +293,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the RECR register /// @param[out] o_delay READ_POINTER_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_read_pointer_delay( const fapi2::buffer& i_data, uint64_t& o_delay ) { i_data.template extractToRight(o_delay); @@ -331,7 +308,7 @@ void get_read_pointer_delay( const fapi2::buffer& i_data, uint64_t& o_ /// @param[in,out] io_data the target data buffer /// @param[in] i_delay READ_POINTER_DLY value (in cycles) to set /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_read_pointer_delay( fapi2::buffer& io_data, const uint64_t i_delay ) { FAPI_INF( "Set READ_POINTER_DLY to %d", i_delay); @@ -339,35 +316,6 @@ void set_read_pointer_delay( fapi2::buffer& io_data, const uint64_t i_ io_data.template insertFromRight(i_delay); } -/// -/// @brief Get the tce correction enable value from RECR -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_data the data buffer containing the RECR register -/// @param[out] o_value TCE_CORRECTION_ENABLE value (on or off) -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > -void get_tce_correction( const fapi2::buffer& i_data, mss::states& o_value ) -{ - o_value = i_data.template getBit() ? mss::states::ON : mss::states::OFF; - - FAPI_INF( "TCE_CORRECTION_ENABLE: %lu", o_value ); -} - -/// -/// @brief Sets tce correction enable in buffer -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in,out] io_data the target data buffer -/// @param[in] i_value TCE_CORRECTION_ENABLE value (on or off) to set -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > -void set_tce_correction( fapi2::buffer& io_data, const mss::states i_value ) -{ - FAPI_INF( "Set TCE_CORRECTION_ENABLE to %lu", i_value); - - io_data.template writeBit(i_value); -} /// /// @brief Get the enable_ue_noise_window value from buffer @@ -376,7 +324,7 @@ void set_tce_correction( fapi2::buffer& io_data, const mss::states i_v /// @param[in] i_data the data buffer containing the RECR register /// @param[out] o_value ENABLE_UE_NOISE_WINDOW value (on or off) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_enable_ue_noise_window( const fapi2::buffer& i_data, mss::states& o_value ) { o_value = (i_data.template getBit()) ? mss::states::ON : mss::states::OFF; @@ -391,7 +339,7 @@ void get_enable_ue_noise_window( const fapi2::buffer& i_data, mss::sta /// @param[in,out] io_data the target data buffer /// @param[in] i_value ENABLE_UE_NOISE_WINDOW value (on or off) to set /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_enable_ue_noise_window( fapi2::buffer& io_data, const mss::states i_value ) { FAPI_INF( "Set ENABLE_UE_NOISE_WINDOW to %lu", i_value); @@ -407,7 +355,7 @@ void set_enable_ue_noise_window( fapi2::buffer& io_data, const mss::st /// @param[in] i_target the target /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target& i_target) { constexpr uint64_t MNFG_REPAIRS_DISABLED_ATTR = 56; @@ -415,15 +363,17 @@ fapi2::ReturnCode setup_read_pointer_delay (const fapi2::Target& i_target) fapi2::buffer l_mnfg_buffer; mss::states l_state = mss::OFF; - FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", mss::c_str(i_target)); + FAPI_TRY( mss::read_recr_register(i_target, l_data ), "%s: Failed read_recr_register", + mss::c_str(i_target)); mss::set_read_pointer_delay(l_data, mss::ON); // Check for manufacturing disable dram repair flag to disable TCE correction FAPI_TRY( mss::mnfg_flags(l_mnfg_buffer), "%s: Failed mnfg_flags check", mss::c_str(i_target) ); l_state = ( l_mnfg_buffer.getBit() ) ? mss::OFF : mss::ON; - mss::set_tce_correction(l_data, l_state); + mss::set_tce_correction(l_data, l_state); - FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", mss::c_str(i_target)); + FAPI_TRY( mss::write_recr_register(i_target, l_data), "%s: Failed write_recr_register", + mss::c_str(i_target)); fapi_try_exit: return fapi2::current_err; @@ -438,7 +388,7 @@ fapi_try_exit: /// @param[out] o_delay the buffer to write the register data into /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode read_dsm0q_register( const fapi2::Target& i_target, fapi2::buffer& o_delay ) { FAPI_TRY( mss::getScom(i_target, TT::DSM0Q_REG, o_delay) ); @@ -457,7 +407,7 @@ fapi_try_exit: /// @param[in] i_delay the buffer that holds the register data to write /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode write_dsm0q_register( const fapi2::Target& i_target, const fapi2::buffer i_delay ) { FAPI_INF( "Change Data State machine register to %d for %s", i_delay, mss::c_str(i_target) ); @@ -475,7 +425,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the DSM0Q register /// @param[out] o_delay WRDONE_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_wrdone_delay( const fapi2::buffer& i_data, uint64_t& o_delay ) { i_data.template extractToRight(o_delay); @@ -490,7 +440,7 @@ void get_wrdone_delay( const fapi2::buffer& i_data, uint64_t& o_delay /// @param[in] i_delay WRDONE_DLY value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer& io_data ) { FAPI_INF( "Set WRDONE_DLY to %d ", i_delay); @@ -506,7 +456,7 @@ void set_wrdone_delay( const uint64_t i_delay, fapi2::buffer& io_data /// @param[in] i_delay WRDONE_DLY value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_wrdone_delay( const fapi2::Target& i_target, const uint64_t i_delay ) { fapi2::buffer l_data; @@ -530,7 +480,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the DSM0Q register /// @param[out] o_delay RDTAG_DLY value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_rdtag_delay( const fapi2::buffer& i_data, uint64_t& o_delay ) { i_data.template extractToRight(o_delay); @@ -545,7 +495,7 @@ void get_rdtag_delay( const fapi2::buffer& i_data, uint64_t& o_delay ) /// @param[in] i_delay RDTAG_DLY value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer& io_data ) { FAPI_DBG( "Set RDTAG_DLY to %d ", i_delay); @@ -562,7 +512,7 @@ void set_rdtag_delay( const uint64_t i_delay, fapi2::buffer& io_data ) /// @param[in] i_delay new RDTAG_DLY value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_rdtag_delay( const fapi2::Target& i_target, const uint64_t i_delay ) { fapi2::buffer l_data; @@ -587,7 +537,7 @@ fapi_try_exit: /// @param[out] o_time the buffer to read the register data into /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode read_farb0q_register( const fapi2::Target& i_target, fapi2::buffer& o_time ) { FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, o_time) ); @@ -606,7 +556,7 @@ fapi_try_exit: /// @param[in] i_delay the buffer containing the data to be written /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode write_farb0q_register( const fapi2::Target& i_target, const fapi2::buffer i_time ) { FAPI_INF( "Change FARB0Q_REG to 0x%016lx for %s", uint64_t(i_time), mss::c_str(i_target) ); @@ -624,7 +574,7 @@ fapi_try_exit: /// @param[in] i_data the data buffer containing the FARB0Q register /// @param[out] o_time RCD_PROTECT_TIME value (in cycles) /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void get_rcd_protect_time( const fapi2::buffer& i_data, uint64_t& o_time ) { i_data.template extractToRight(o_time); @@ -640,7 +590,7 @@ void get_rcd_protect_time( const fapi2::buffer& i_data, uint64_t& o_ti /// @param[in] i_delay RCD Protect Time value (in cycles) to set /// @param[in,out] io_data the target data buffer /// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = portTraits > void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer& io_data ) { FAPI_DBG( "Set RCD_PROTECT_TIME to %d ", i_time); @@ -656,7 +606,7 @@ void set_rcd_protect_time( const uint64_t i_time, fapi2::buffer& io_da /// @param[in] i_time RCD Protect Time value (in cycles) to set /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_rcd_protect_time( const fapi2::Target& i_target, const uint64_t i_time ) { fapi2::buffer l_data; @@ -673,28 +623,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief Change the state of the port_fail_disable bit -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// @note Disable Port Fail after recurring RCD errors. -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode change_port_fail_disable( const fapi2::Target& i_target, states i_state ) -{ - fapi2::buffer l_data; - - FAPI_DBG("Change port fail disable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB0Q_REG, l_data) ); - l_data.writeBit(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB0Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} /// /// @brief Change the state of the RCD recovery bit @@ -704,7 +632,7 @@ fapi_try_exit: /// @param[in] i_state the state /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_rcd_recovery_disable( const fapi2::Target& i_target, states i_state ) { fapi2::buffer l_data; @@ -726,7 +654,7 @@ fapi_try_exit: /// @param[in] i_state the state /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode change_oe_always_on( const fapi2::Target& i_target, states i_state ) { fapi2::buffer l_data; @@ -740,50 +668,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief Change the state of the addr_mux_sel bit -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode change_addr_mux_sel( const fapi2::Target& i_target, states i_state ) -{ - fapi2::buffer l_data; - - FAPI_DBG("Change addr_mux_sel to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::FARB5Q_REG, l_data) ); - l_data.writeBit(i_state); - FAPI_TRY( mss::putScom(i_target, TT::FARB5Q_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Change the state of the MC Refresh enable bit -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @param[in] i_state the state -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode change_refresh_enable( const fapi2::Target& i_target, states i_state ) -{ - fapi2::buffer l_data; - - FAPI_DBG("Change refresh enable to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); - FAPI_TRY( mss::getScom(i_target, TT::REFRESH_REG, l_data) ); - l_data.writeBit(i_state); - FAPI_TRY( mss::putScom(i_target, TT::REFRESH_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} /// /// @brief Enable the MC Periodic calibration functionality @@ -792,7 +676,7 @@ fapi_try_exit: /// @param[in] i_target the target /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode enable_periodic_cal( const fapi2::Target& i_target ); /// @@ -803,45 +687,6 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target& i_target ); template<> fapi2::ReturnCode enable_periodic_cal( const fapi2::Target& i_target ); -/// -/// @brief Enable Read ECC checking -/// @tparam T the fapi2 target type of the target -/// @tparam TT the class traits for the port -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode enable_read_ecc( const fapi2::Target& i_target ) -{ - fapi2::buffer l_data; - - uint8_t l_sim = 0; - FAPI_TRY( mss::is_simulation(l_sim) ); - - FAPI_DBG("Enable Read ECC %s", mss::c_str(i_target)); - - FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); - l_data.clearBit(); - l_data.clearBit(); - - // VBU tests assume good ECC and we don't have good ECC (since we're not writing everything) - // so we can't run with address checking. Disable address checking in sim. - l_data.writeBit(l_sim ? 0 : 1); - - // The preferred operating mode is 11 (INVERT_DATA_TOGGLE_CHECKS) which stores data complemented - // (because most bits are '0', and the dram bus pulls up, so transmitting 1s is least power) but - // still flips the inversion of check bits to aid RAS. Per Brad Michael 12/15 - // Leave un-inverted for sim. This allows the DIMM loader to write 0's and effect good ECC - l_data.insertFromRight(l_sim ? 0b00 : 0b11); - - // bits: 60 MBSTRQ_CFG_MAINT_RCE_WITH_CE - // cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. - - FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} // // We expect to come in to draminit with the following setup: @@ -860,7 +705,7 @@ fapi_try_exit: // This is in this header as it's hoped to be able to be shared. Seems to make more // Might make more sense in p9_mss_draminit.C ... BRS /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > inline fapi2::ReturnCode draminit_entry_invariant( const fapi2::Target& i_target ) { fapi2::buffer l_data; @@ -889,7 +734,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// @note this might need a port id added for Centaur/MBA controllers /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode drive_mem_clks( const fapi2::Target& i_target, const uint64_t i_pclk, const uint64_t i_nclk ) { fapi2::buffer l_data; @@ -918,7 +763,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// @note this might need a port id added for Centaur/MBA controllers /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode ddr_resetn( const fapi2::Target& i_target, const bool i_state ) { fapi2::buffer l_data; @@ -950,36 +795,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief Apply mark store bits from module VPD -/// @tparam T, the fapi2 target type of the target -/// @tparam TT, the class traits for the port -/// @param[in] i_target A target representing a port -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, typename TT = portTraits > -fapi2::ReturnCode apply_mark_store( const fapi2::Target& i_target ) -{ - FAPI_INF("Enable marks from MVPD"); - - uint32_t l_fwms[MARK_STORE_COUNT]; - - FAPI_TRY( mss::mvpd_fwms(i_target, &(l_fwms[0])) ); - - for (size_t l_mark = 0; l_mark < MARK_STORE_COUNT; ++l_mark) - { - if (l_fwms[l_mark] != 0) - { - fapi2::buffer l_fwms_data; - l_fwms_data.insertFromRight < MCA_FWMS0_MARK, MCA_FWMS0_EXIT_1 - MCA_FWMS0_MARK + 1 > (l_fwms[l_mark]); - FAPI_TRY( mss::putScom(i_target, MCA_FWMS0 + l_mark, l_fwms_data) ); - } - } - -fapi_try_exit: - return fapi2::current_err; -} - /// /// @brief Reset the ZCAL config register. /// @warning This maps PHY rank numbers per target @@ -987,7 +802,7 @@ fapi_try_exit: /// @param[in] i_target A target representing a port /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename TT = portTraits > +template< fapi2::TargetType T, typename TT = portTraits > fapi2::ReturnCode reset_zqcal_config( const fapi2::Target& i_target ) { fapi2::buffer l_phy_zqcal_config; @@ -1016,7 +831,7 @@ fapi_try_exit: /// inline fapi2::ReturnCode configure_wrq(const fapi2::Target& i_target, const mss::states i_state) { - typedef portTraits TT; + typedef portTraits TT; fapi2::buffer l_data; @@ -1064,7 +879,7 @@ fapi_try_exit: /// inline fapi2::ReturnCode configure_rrq(const fapi2::Target& i_target, const mss::states i_state) { - typedef portTraits TT; + typedef portTraits TT; fapi2::buffer l_data; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index 9918c43ee..3e4f32c5b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -14097,28 +14097,6 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory power control settings programmed during IPL Used by OCC when exiting -/// idle power-save -/// mode -/// -inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), - o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)", - uint64_t(fapi2::current_err)); - return fapi2::current_err; -} - /// /// @brief ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED getter /// @param[out] uint8_t& reference to store the value @@ -21246,6 +21224,51 @@ fapi_try_exit: } +/// +/// @brief ATTR_MEM_MRW_IS_PLANAR getter +/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (PROC_CHIP) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Indicates if the DIMM connected to this controller are in a planar +/// configuration +/// +inline fapi2::ReturnCode mem_mrw_is_planar(const fapi2::Target& i_target, + uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_MRW_IS_PLANAR, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MEM_MRW_IS_PLANAR: 0x%lx", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Memory power control settings programmed during IPL Used by OCC when exiting +/// idle power-save +/// mode +/// +inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + + } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index ca2655f88..03408da9d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -73,7 +73,6 @@ enum sizes NUM_MRW_FREQS = 4, ///< Used for ATTR_MSS_MRW_SUPPORTED_FREQ - MARK_STORE_COUNT = 8, ///< Elements in a VPD mark/store array BAD_DQ_BYTE_COUNT = 10, ///< Elements in a BAD_DQ_BITMAP attribute array ROW_REPAIR_BYTE_COUNT = 4, ///< Elements in a ROW_REPAIR_DATA attribute array. @@ -215,29 +214,6 @@ enum ffdc_function_codes MREP_CALL_OUT = 131, }; -enum states -{ - LOW = 0, - HIGH = 1, - START = 1, - STOP = 0, - START_N = 0, - STOP_N = 1, - ON = 1, - OFF = 0, - ON_N = 0, - OFF_N = 1, - YES = 1, - NO = 0, - YES_N = 0, - NO_N = 1, - // Uses "_" in the name for INVALID as INVALID is defined as a macro in the - // FSP code. If we just use INVALID as an enum name, then the preprocessor - // compile phase changes it to be the macro. - _INVALID_ = 0xFF, - NO_CHIP_SELECT_ACTIVE = 0xFF, -}; - // Static consts describing the bits used in the cal_step_enable attribute // These are bit positions. 0 is the left most bit. enum cal_steps : uint64_t diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C index d6c6f3a42..37d03bb9b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -156,7 +156,8 @@ fapi2::ReturnCode str_non_tsv_parity(const fapi2::Target // STR can be enabled via two attributes - ATTR_MSS_MRW_POWER_CONTROL_REQUESTED or ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED uint8_t l_power_control = 0; uint8_t l_idle_power_control = 0; - FAPI_TRY( mss::mrw_power_control_requested(l_power_control) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + l_power_control) ); FAPI_TRY( mss::mrw_idle_power_control_requested(l_idle_power_control) ); // If the workaround is not needed, skip it diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C index 1a6f53670..e7c46f515 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -208,9 +208,9 @@ fapi2::ReturnCode broadcast_out_of_sync( const fapi2::Target l_recr_buffer; // Set UE noise window for workaround - mss::read_recr_register(p, l_recr_buffer); + mss::read_recr_register(p, l_recr_buffer); mss::set_enable_ue_noise_window(l_recr_buffer, i_value); - mss::write_recr_register(p, l_recr_buffer); + mss::write_recr_register(p, l_recr_buffer); } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C index d0362d456..d205e1107 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -41,6 +41,7 @@ #include #include #include +#include using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -172,7 +173,7 @@ extern "C" // before the RCD/MRS CCSs for (const auto& p : l_mcas) { - FAPI_TRY( change_addr_mux_sel(p, mss::LOW), + FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW), "%s Failed change_addr_mux_sel in p9_mss_draminit", mss::c_str(i_target) ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index 18a0c2160..91e8ff18e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -114,11 +114,11 @@ extern "C" // mode prior to running memory diagnostics. This step may be superfluous but not harmful.) // Note: addr_mux_sel is set low in p9_mss_draminit(), however that might be a work-around so we // set it low here kind of like belt-and-suspenders. BRS - FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW), + FAPI_TRY( mss::change_addr_mux_sel(p, mss::LOW), "%s Failed to change_addr_mux_sel", mss::c_str(i_target) ); // Re-enable port fails. Turned off in draminit_training - FAPI_TRY( mss::change_port_fail_disable(p, mss::OFF ), + FAPI_TRY( mss::change_port_fail_disable(p, mss::OFF ), "%s Failed to change_port_fail_disable", mss::c_str(i_target) ); // MC work around for OE bug (seen in periodics + PHY) @@ -131,7 +131,8 @@ extern "C" // Start the refresh engines by setting MBAREF0Q(0) = “1”. Note that the remaining bits in // MBAREF0Q should retain their initialization values. - FAPI_TRY( mss::change_refresh_enable(p, mss::HIGH), "%s Failed change_refresh_enable", mss::c_str(i_target) ); + FAPI_TRY( mss::change_refresh_enable(p, mss::HIGH), "%s Failed change_refresh_enable", + mss::c_str(i_target) ); // Power management is handled in the init file. (or should be BRS) @@ -139,10 +140,10 @@ extern "C" FAPI_TRY( mss::enable_periodic_cal(p), "%s Failed enable_periodic_cal", mss::c_str(i_target) ); // Step Six: Setup Control Bit ECC - FAPI_TRY( mss::enable_read_ecc(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::enable_read_ecc(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); // apply marks from MVPD - FAPI_TRY( mss::apply_mark_store(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::apply_mark_store(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); } // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index da65aaf12..5fbedcf7c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -144,7 +144,7 @@ extern "C" // Disable port fails as it doesn't appear the MC handles initial cal timeouts // correctly (cal_length.) BRS, see conversation with Brad Michael - FAPI_TRY( mss::change_port_fail_disable(p, mss::ON ), "Error in p9_mss_draminit_training" ); + FAPI_TRY( mss::change_port_fail_disable(p, mss::ON ), "Error in p9_mss_draminit_training" ); // The following registers must be configured to the correct operating environment: diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index abd4fca50..2e8fb7167 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -5,7 +5,7 @@ - + @@ -241,21 +241,6 @@ - - ATTR_MSS_MRW_POWER_CONTROL_REQUESTED - TARGET_TYPE_SYSTEM - - Memory power control settings programmed during IPL - Used by OCC when exiting idle power-save mode - - uint8 - OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03 - - OFF - - mrw_power_control_requested - - ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED TARGET_TYPE_SYSTEM -- cgit v1.2.1