From 3109d56eadab9663893c1b1cd7ac583684e7d877 Mon Sep 17 00:00:00 2001 From: Yue Du Date: Thu, 25 Aug 2016 14:04:06 -0500 Subject: cache/core/l2_stopclocks updates patchset 1: skip l2_stopclocks if ex_select is 0 patchset 2: check power state before execute hwp patchset 3: fix syntax typos from patch 2 update patchset 4: add chiplet accessibility check patchset 5: add possible counter to CME PCBMUX patchset 6: add skipping message on check patchset 7: change polling timout method patchset 8: add a missing comma patchset 9: fix ffdc patchset 10:roll back cme pcbmux counter until check to ensure cme accessibility patchset 11:rebased patchset 12:initial checkin of ppe state handling patchset 13:checkin new clk_ctrl_state procedure patchset 14:add attribute xml for new procedure patchset 15:fix calling the p9_common_clk_ctrl_state patchset 16:Matt rebase patchset 17:Warning instead of fail with error on check delete common C file, include only header Change-Id: I26c171400b07943561a3c44e5623a8826c666c6f Original-Change-Id: I14c9480ac0931ac7f8b456f193148ceb3b939947 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28808 Dev-Ready: YUE DU Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Matt K. Light Tested-by: PPE CI Reviewed-by: Gregory S. Still Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36105 Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Reviewed-by: Daniel M. Crowell --- .../procedures/hwp/lib/p9_common_clk_ctrl_state.H | 123 +++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 src/import/chips/p9/procedures/hwp/lib/p9_common_clk_ctrl_state.H (limited to 'src/import/chips/p9/procedures') diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_common_clk_ctrl_state.H b/src/import/chips/p9/procedures/hwp/lib/p9_common_clk_ctrl_state.H new file mode 100644 index 000000000..515435038 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/lib/p9_common_clk_ctrl_state.H @@ -0,0 +1,123 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/lib/p9_common_clk_ctrl_state.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_common_clk_ctrl_state.H +/// @brief Check cache/core clock controller status +/// +/// Procedure Summary: + +// *HWP HWP Owner : David Du +// *HWP Backup HWP Owner : Greg Still +// *HWP FW Owner : Sangeetha T S +// *HWP Team : PM +// *HWP Consumed by : HB:PERV +// *HWP Level : 2 + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- + +#include +#include +#include + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +const uint64_t NET_CTRL0[2] = { C_NET_CTRL0, EQ_NET_CTRL0}; +const uint64_t PPM_PFSNS[2] = { C_PPM_PFSNS, EQ_PPM_PFSNS}; + +//----------------------------------------------------------------------------- +// Template Procedure +//------------------------------------------------------------------------------ + +template +fapi2::ReturnCode +p9_common_clk_ctrl_state( + const fapi2::Target& i_target) +{ + FAPI_INF(">>p9_common_clk_ctrl_state"); + fapi2::buffer l_data64; + uint32_t l_type = 0; // Assumes core + + if((i_target.getType() & fapi2::TARGET_TYPE_EQ)) + { + l_type = 1; + } + + FAPI_DBG("Check chiplet accessibility via NET_CTRL0[0,1,16,25,26]"); + FAPI_TRY(getScom(i_target, NET_CTRL0[l_type], l_data64)); + + if (l_data64.getBit<25>()) + { + FAPI_INF("WARNING: Chiplet appears Offline as PCB Fence is up. Skipping"); + fapi2::current_err = fapi2::FAPI2_RC_FALSE; + goto fapi_try_exit; + } + + if (l_data64.getBit<0>() == 0) + { + FAPI_INF("WARNING: Chiplet Disabled. Assume being Partial Bad. Skipping"); + fapi2::current_err = fapi2::FAPI2_RC_FALSE; + goto fapi_try_exit; + } + + if (l_data64.getBit<1>()) + { + FAPI_INF("WARNING: Chiplet in fixed state as PcbEpReset is on. Skipping"); + fapi2::current_err = fapi2::FAPI2_RC_FALSE; + goto fapi_try_exit; + } + + if (l_data64.getBit<26>()) + { + FAPI_INF("WARNING: Chiplet Elec Fence is up. PCB path blocked. Skipping"); + fapi2::current_err = fapi2::FAPI2_RC_FALSE; + goto fapi_try_exit; + } + + if (l_data64.getBit<16>()) + { + FAPI_INF("WARNING: Chiplet VitalClk off. ClkCtrl inaccessible. Skipping"); + fapi2::current_err = fapi2::FAPI2_RC_FALSE; + goto fapi_try_exit; + } + + FAPI_DBG("Check chiplet power state via PPM_PFSNS[1]"); + FAPI_TRY(getScom(i_target, PPM_PFSNS[l_type], l_data64)); + + if (l_data64.getBit<1>()) + { + FAPI_INF("WARNING: Chiplet out of power while Elec Fence down. Skipping"); + fapi2::current_err = fapi2::FAPI2_RC_FALSE; + goto fapi_try_exit; + } + +fapi_try_exit: + + FAPI_INF("<