From eb3d4239bbecc49ac6f6d3a78ef196136caea07c Mon Sep 17 00:00:00 2001 From: Emmanuel Sacristan Date: Tue, 30 Jul 2019 13:18:01 -0500 Subject: adding iss 768 init for p9 behaviour in nmmu Change-Id: I41d302272200ddc37276f56e238ccab8ed768163 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81386 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: Adam S Hale Reviewed-by: JAKE C TRUELOVE Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81402 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M Crowell --- .../xml/attribute_info/chip_ec_attributes.xml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/import/chips/p9/procedures/xml') diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 0c2eb62bd..a3e660b90 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -3164,6 +3164,23 @@ + + + ATTR_CHIP_EC_FEATURE_NMMU_AX1_ISS768_FIX_DIS + TARGET_TYPE_PROC_CHIP + + NMMU disables seg fault generation for radix access to DR=1, HV=1 with lpid !=0. + + + + ENUM_ATTR_NAME_AXONE + + 0x10 + GREATER_THAN_OR_EQUAL + + + + ATTR_CHIP_EC_FEATURE_NMMU_PWC_DIS_DD2 -- cgit v1.2.1