From 6650adcec6acc4358ded7a9e2256d096123fde8b Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Tue, 28 Nov 2017 14:28:49 -0600 Subject: Updates training advanced and adds custom WR CTR Breaks apart and reorganizes training advanced code Adds custom pattern WR CTR in training advanced Updates custom WR/RD patterns for characterization data Change-Id: I3fc6e515f0ae2f853ce53a198a82b7513da4eea5 CQ:SW411492 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50118 Tested-by: FSP CI Jenkins Dev-Ready: STEPHEN GLANCY Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: Louis Stermole Reviewed-by: ANDRE A. MARIN Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50141 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- .../xml/attribute_info/memory_mcs_attributes.xml | 30 +++++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) (limited to 'src/import/chips/p9/procedures/xml') diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 9f80daa43..eb57d043f 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1951,8 +1951,9 @@ [17] WRITE_CTR [18] COARSE_WR [19] COARSE_RD - [20] TRAINING_ADV Only set for DD2.* machines - [21]:[31] Reserved for future use + [20] TRAINING_ADV_RD Only set for DD2.* machines + [21] TRAINING_ADV_WR Only set for DD2.* machines + [22]:[31] Reserved for future use COARSE_WR and COARSE_RD will be consumed together to form COARSE_LVL. @@ -1973,7 +1974,7 @@ TARGET_TYPE_MCS Special training pattern used in draminit_training_advance. - Used for custom pattern write + Used for custom pattern read There can be two patterns used here. This attribute is before swizzling for endianness of the registers. CODE WILL SWIZZLE FOR THE SYSTEM @@ -1997,7 +1998,7 @@ TARGET_TYPE_MCS Special training backup pattern - Used for custom_pattern_write in draminit_training_advance. + Used for custom_pattern_read in draminit_training_advance. If the main patterns fail, the code will try running this pattern Used for read centering There can be two patterns used here. @@ -2018,6 +2019,27 @@ custom_training_adv_backup_patterns + + ATTR_MSS_CUSTOM_TRAINING_ADV_WR_PATTERN + TARGET_TYPE_MCS + + Special training pattern used in draminit_training_advance. + Used for custom pattern write + Due to hardware limitations, only one 8-bit pattern can be used + This attribute is before swizzling for endianness of the registers. + CODE WILL SWIZZLE FOR THE SYSTEM + If this attribute is set to 0, using the default values of: + 0x9A + Set to default in eff_config + + uint8 + + DEFAULT = 0x69 + + 2 + custom_training_adv_wr_pattern + + ATTR_MSS_VREF_CAL_ENABLE TARGET_TYPE_MCS -- cgit v1.2.1