From 40bcbd0f3a78e74a6c23c050f7cef854cc2c283a Mon Sep 17 00:00:00 2001 From: Tsung Yeung Date: Tue, 19 Mar 2019 09:21:53 -0400 Subject: Enable median rank wr_vref value on NVDIMM - The NVDIMM restore procedure is required to restore the wr vref values. The current method is to latch in the per-dram wr vref value with PDA. However, this requires multiple CCS sequences due to hardware limitation and would break refresh timing between sequences, introduce possible UEs. To get around this, we will use the median value of all the drams per rank-pair instead of per-dram value. Previous attempt was to use average value but after the speaking with Stephen G. median value is a better approach due to the possibility that bad vref value from failing dram - Added NVDIMM-specifc CCS execute procedure Change-Id: Ie7d1e063c423a4374ca22422395ee5524d70a124 CQ:SW459457 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74753 Tested-by: FSP CI Jenkins Reviewed-by: Louis Stermole Reviewed-by: STEPHEN GLANCY Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74790 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../xml/error_info/p9_memory_mss_draminit_training.xml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src/import/chips/p9/procedures/xml') diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml index 7ac07623b..d7bb833cd 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml @@ -5,7 +5,7 @@ - + @@ -820,4 +820,12 @@ + + RC_MSS_RP_OUT_OF_RANGE + + An informational callout for rank-pair value out of range + + RP + + -- cgit v1.2.1