From b4a8d8383f5fcf1099dcb79de85b4352da1fa56d Mon Sep 17 00:00:00 2001 From: Greg Still Date: Tue, 3 May 2016 15:56:40 -0500 Subject: Pstate Parameter Block structure - Added VDM and Droop attributes refined in design sessions - Refined OCC, Local (CME) and Global (PGPE) content - Additional attributes to structure updates - Moved freqeuncy bias attributes from "EXT" to applying to both external (Global) and internal (Local) computations (eg remove EXT_ from the name) - Add resonant clocking attributes - Add iVRM attributes and content to p9_pstates.h and INT biasing attributes to XML - Add generated Pstate output structure - Moved ATTR_DPLL_DIVIDER to p9_pm_hwp_attributes.xml as it is written with default vs relying on platform from necessarily providing it.. - Change ATTR_DPLL_DIVIDER default access to check for 0 value to then set default value - Added temporaty HB attributes - Added ATTR_VDM_ENABLE plus rebase - Deal with HB CI warnings - Rebase Change-Id: I435bcbbbba0006718211341322d26c6d98bb7dec RTC: 153217 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24904 Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Gregory S. Still Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24907 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../xml/attribute_info/pm_hwp_attributes.xml | 59 ++++++++++++++++------ 1 file changed, 43 insertions(+), 16 deletions(-) (limited to 'src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml') diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml index 7455b1ba6..ec77ed527 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_hwp_attributes.xml @@ -21,15 +21,32 @@ + + + ATTR_PROC_DPLL_DIVIDER + TARGET_TYPE_PROC_CHIP + The product of the DPLL internal prescalar divide + (CD_DIV124_DC) and the output divider(CD_DPLLOUT124_DC). This estalishes + the step size of the DPLL in terms of this number divided into the + processor reference clock. + + if 0, consuming procedures will assume a default of 8. + + Provided to override default value + + uint32 + + + ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET TARGET_TYPE_PROC_CHIP Set by p9_hcode_image build with the offset value from the HOMER base where the SGPE Boot Copier interrupt vectors reside. This - value must be 512B aligned. The HOMER base address will be pre-establish - in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The SGPE - will be Sreset after this value is established. + value must be 512B aligned. The HOMER base address will be pre-establish + in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The SGPE + will be Sreset after this value is established. uint32 @@ -40,13 +57,13 @@ TARGET_TYPE_PROC_CHIP Set by p9_hcode_image build with the offset value from the HOMER base where the PGPE Boot Copier interrupt vectors reside. This - value must be 512B aligned. The HOMER base address will be pre-establish - in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The PGPE + value must be 512B aligned. The HOMER base address will be pre-establish + in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The PGPE will be Sreset after this value is established uint32 - + ATTR_OCC_LFIR @@ -73,8 +90,10 @@ TARGET_TYPE_PROC_CHIP 0 = OCC has never been loaded and FIR Masks have never been initialized, - 1 = FIR masks have been initialized and the hardware should reflect correct values, - 2 = FIR masks have been initialized but the current hardware state is the reset value + 1 = FIR masks have been initialized and the hardware should reflect + correct values, + 2 = FIR masks have been initialized but the current hardware state is the + reset value uint8 @@ -136,7 +155,8 @@ ATTR_C0_EXEC_HASCLOCKS TARGET_TYPE_EX - Indicates the execution units in core 0 have clocks running and scommable + Indicates the execution units in core 0 have clocks running + and scommable uint8 @@ -145,7 +165,8 @@ ATTR_C1_EXEC_HASCLOCKS TARGET_TYPE_EX - Indicates the execution units in core 1 have clocks running and scommable + Indicates the execution units in core 1 have clocks running + and scommable uint8 @@ -154,7 +175,8 @@ ATTR_C0_PC_HASCLOCKS TARGET_TYPE_EX - Indicates the core pervasive unit in core 0 has clocks running and scommable + Indicates the core pervasive unit in core 0 has clocks + running and scommable uint8 @@ -163,7 +185,8 @@ ATTR_C1_PC_HASCLOCKS TARGET_TYPE_EX - Indicates the core pervasive unit in core 1 has clocks running and scommable + Indicates the core pervasive unit in core 1 has clocks + running and scommable uint8 @@ -172,7 +195,8 @@ ATTR_L2_HASPOWER TARGET_TYPE_EX - Indicates L2 has power and has valid latch state that could be scanned + Indicates L2 has power and has valid latch state that could + be scanned uint8 @@ -181,7 +205,8 @@ ATTR_L3_HASPOWER TARGET_TYPE_EX - Indicates L3 has power and has valid latch state that could be scanned + Indicates L3 has power and has valid latch state that could + be scanned uint8 @@ -190,7 +215,8 @@ ATTR_C0_HASPOWER TARGET_TYPE_EX - Indicates core 0 has power and has valid latch state that could be scanned + Indicates core 0 has power and has valid latch state that + could be scanned uint8 @@ -199,7 +225,8 @@ ATTR_C1_HASPOWER TARGET_TYPE_EX - Indicates core 1 has power and has valid latch state that could be scanned + Indicates core 1 has power and has valid latch state that + could be scanned uint8 -- cgit v1.2.1