From d8243ae68238a8697b7bd08c98d9f204c13de13c Mon Sep 17 00:00:00 2001 From: Jacob Harvey Date: Wed, 29 Jun 2016 11:12:59 -0500 Subject: Implementing thermal_init Change-Id: I0fc6f6ab6f209f7399d0f5369b03a4504838a026 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26739 Tested-by: Jenkins Server Reviewed-by: Brian R. Silver Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN Reviewed-by: JACOB L. HARVEY Reviewed-by: Jennifer A. Stofer --- .../chips/p9/procedures/hwp/memory/lib/mc/mc.C | 144 ++++++--------------- .../chips/p9/procedures/hwp/memory/lib/mc/mc.H | 55 ++++---- .../chips/p9/procedures/hwp/memory/lib/mc/xlate.C | 20 ++- .../hwp/memory/lib/mss_attribute_accessors.H | 21 --- .../p9/procedures/hwp/memory/lib/utils/find.H | 45 +++++-- .../p9/procedures/hwp/memory/p9_mss_draminit_mc.C | 4 +- .../p9/procedures/hwp/memory/p9_mss_scominit.C | 1 + .../p9/procedures/hwp/memory/p9_mss_thermal_init.C | 18 ++- .../p9/procedures/hwp/memory/p9_mss_thermal_init.H | 3 +- .../procedures/hwp/memory/p9_mss_thermal_init.mk | 4 +- 10 files changed, 127 insertions(+), 188 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index 71b75fcaa..c8a58a083 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -22,17 +22,15 @@ /// @brief Subroutines to manipulate the memory controller /// // *HWP HWP Owner: Brian Silver -// *HWP HWP Backup: Andre Marin +// *HWP HWP Backup: Jacob Harvey // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB #include -#include - #include -#include #include +#include using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCS; @@ -124,16 +122,16 @@ fapi2::ReturnCode dump_regs( const fapi2::Target& i_target ) {"MCS_MCWATCNTL", MCS_MCWATCNTL }, }; - for (auto r : l_mcs_registers) + for (const auto& r : l_mcs_registers) { fapi2::buffer l_data; FAPI_TRY( mss::getScom(i_target, r.second, l_data) ); FAPI_DBG("dump %s: 0x%016lx 0x%016lx", r.first, r.second, l_data); } - for (auto p : i_target.getChildren()) + for (const auto& p : find_targets(i_target)) { - for (auto r : l_mba_registers) + for (const auto r : l_mba_registers) { fapi2::buffer l_data; FAPI_TRY( mss::getScom(p, r.second, l_data) ); @@ -145,131 +143,65 @@ fapi_try_exit: return fapi2::current_err; } +namespace mc +{ + /// -/// @brief Perform initializations for the MC (MCA) -/// @param[in] i_target, the MCA to initialize -/// @return FAPI2_RC_SUCCESS iff ok +/// @brief safemode throttle values defined from MRW attributes +/// @param[in] i_target the MCA target +/// @return fapi2::FAPI2_RC_SUCCESS if ok +/// @note sets safemode values for emergency mode and regular throttling /// -template<> -fapi2::ReturnCode mc::scominit(const fapi2::Target& i_target) +fapi2::ReturnCode thermal_throttle_scominit (const fapi2::Target& i_target) { uint32_t l_throttle_denominator = 0; - FAPI_TRY( mss::runtime_mem_m_dram_clocks(i_target, l_throttle_denominator) ); - - // #Register Name Final Arb Parms - // #Mnemonic MBA_FARB0Q - // #Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use - // #Description FARB command control - // #1. FARB0 bit 38: cfg_parity_after_cmd - // # - set this bit if DDR3 and (RDIMM or LDRIMM) - // - // # - clear this bit if DDR4 and (RDIMM or LDRIMM) - // #2. FARB0 bit 60: cfg_ignore_rcd_parity_err - // # - clear this bit if (RDIMM or LDRIMM) - // #3. FARB0 bit 61: cfg_enable_rcd_rw_retry - // # - set this bit if (RDIMM or LDRIMM) + FAPI_TRY( mss::mem_m_dram_clocks( i_target, l_throttle_denominator) ); - // Nimbus is always LR/RDIMM, DDR4. - // Not sure what happened to cfg_ignore_rcd_parity_err, cfg_enable_rcd_rw_retry - perhaps they're always ok since we don't - // support anything else? { fapi2::buffer l_data; + FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB3Q, l_data)); - l_data.setBit(); - FAPI_TRY( mss::putScom(i_target, MCA_MBA_FARB0Q, l_data) ); - } - - { - // FABR1Q - Chip ID bits - } - { - // FARB2Q - ODT bits - } - - // #Register Name N/M Throttling Control - // #Mnemonic MBA_FARB3Q - // #Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use - // #Description N/M throttling control (Centaur only) - // # 0:14 cfg_nm_n_per_mba MSS_MEM_THROTTLED_N_COMMANDS_PER_MBA (Centaur) - // # 15:30 cfg_nm_n_per_chip MSS_MEM_THROTTLED_N_COMMANDS_PER_CHIP (Centaur) - // # 0:14 cfg_nm_n_per_slot MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT (Nimbus) - // # 15:30 cfg_nm_n_per_port MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT (Nimbus) - // # 31:44 cfg_nm_m MSS_MEM_THROTTLED_M_DRAM_CLOCKS - // # 51 cfg_nm_per_slot_enabled 1 (not on Nimbus?) - // # 52 cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else (not on Nimbus?) - // #cfg_nm_ras_weight, bits 45:47 = ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT - // #cfg_nm_cas_weight, bits 48:50 = ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT - { - fapi2::buffer l_data; - uint32_t l_throttle_per_slot = 0; uint32_t l_throttle_per_port = 0; - uint8_t l_ras_weight = 0; - uint8_t l_cas_weight = 0; - FAPI_TRY( mss::runtime_mem_throttled_n_commands_per_slot(i_target, l_throttle_per_slot) ); - FAPI_TRY( mss::runtime_mem_throttled_n_commands_per_port(i_target, l_throttle_per_port) ); - FAPI_TRY( mss::throttle_control_ras_weight(i_target, l_ras_weight) ); - FAPI_TRY( mss::throttle_control_cas_weight(i_target, l_cas_weight) ); + FAPI_TRY( mss::mrw_safemode_mem_throttled_n_commands_per_port( l_throttle_per_port) ); - l_data.insertFromRight(l_throttle_per_slot); + l_data.insertFromRight(l_throttle_per_port); l_data.insertFromRight(l_throttle_per_port); l_data.insertFromRight(l_throttle_denominator); - l_data.insertFromRight(l_ras_weight); - l_data.insertFromRight(l_ras_weight); + + l_data.clearBit(); FAPI_TRY( mss::putScom(i_target, MCA_MBA_FARB3Q, l_data) ); - } - // Doesn't appear to be a row-hammer-mode in Nimbus - // # -- bits 27:41 (cfg_emer_n) = ATTR_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_SLOT - // # -- bits 42:55 (cfg_emer_m) = ATTR_MRW_MEM_THROTTLED_M_DRAM_CLOCKS + } { fapi2::buffer l_data; uint32_t l_throttle_per_slot = 0; - FAPI_TRY( mss::mrw_safemode_mem_throttled_n_commands_per_slot(l_throttle_per_slot) ); + FAPI_TRY( mss::mrw_safemode_mem_throttled_n_commands_per_port(l_throttle_per_slot) ); + FAPI_TRY( mss::getScom(i_target, MCA_MBA_FARB4Q, l_data) ); l_data.insertFromRight(l_throttle_denominator); l_data.insertFromRight(l_throttle_per_slot); - FAPI_TRY( mss::putScom(i_target, MCA_MBA_FARB4Q, l_data) ); } - - { - // TMR0Q - DDR data bus timing parameters - } - - { - // TMR1Q - DDR bank busy parameters - } - - { - // DSM0Q - Data State Machine Configurations - } - - { - // MBAREF0Q mba01 refresh settings - } - - { - // MBAPC0Q power control settings reg 0 - // MBAPC1Q power control settings reg 1 - } - - { - // MBAREF1Q MBA01 Rank-to-primary-CKE mapping table - // Doesn't exist in Nimbus. Leaving this as a comment to note that we didn't forget it. - // CKEs are fixed to chip selects for all P9 configs - } - - { - // CAL0Q (this timer to be used for zq cal) - // CAL1Q (this timer to be used for mem cal) - // CAL3Q (this timer to be used for mem cal) - } - fapi_try_exit: return fapi2::current_err; } - +/// +/// @brief Disable emergency mode throttle for thermal_init +/// @param[in] i_target the MCS target +/// @return fapi2::FAPI2_RC_SUCCESS if ok +/// @note Clears MCMODE0_ENABLE_EMER_THROTTLE bit in MCSMODE0 +/// +fapi2::ReturnCode disable_emergency_throttle (const fapi2::Target& i_target) +{ + fapi2::buffer l_data; + FAPI_TRY( mss::getScom(i_target, MCS_MCMODE0, l_data)); + l_data.clearBit(); + FAPI_TRY( mss::putScom(i_target, MCS_MCMODE0, l_data)); +fapi_try_exit: + return fapi2::current_err; } +} // namespace mc +} //close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H index 883e1afc4..fe907b38d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H @@ -143,36 +143,33 @@ enum MAX_TRANSLATIONS = 31, }; -/// -/// @class mss::mc -/// @brief The memory controller class -/// @tparam T the fapi2::TargetType of the controller -/// -template< fapi2::TargetType T > -class mc +namespace mc { - public: - /// - /// @brief Perform initializations for the MC - /// @tparam T the fapi2::TargetType - /// @param[in] i_target the target which has the MCs to initialize - /// @return FAPI2_RC_SUCCESS iff ok - /// - fapi2::ReturnCode scominit(const fapi2::Target& i_target); - - /// - /// @brief Perform initializations of the MC translation - /// @tparam P the fapi2::TargetType of the port - /// @tparam TT the typename of the traits - /// @param[in] i_target the target which has the MCA to map - /// @return FAPI2_RC_SUCCESS iff ok - /// - template< fapi2::TargetType P, typename TT = mcTraits > - fapi2::ReturnCode setup_xlate_map(const fapi2::Target

& i_target); - -}; - -} +/// +/// @brief safemode throttle values defined from MRW attributes +/// @param[in] i_target the MCA target +/// @return FAPI2_RC_SUCCESS iff ok +/// @note sets safemode values for emergency mode and regular throttling +/// +fapi2::ReturnCode thermal_throttle_scominit (const fapi2::Target& i_target); +/// +/// @brief Disable emergency mode throttle for thermal_init +/// @param[in] i_target the MCS target +/// @return FAPI_RC_SUCCESS iff ok +/// @note Clears MCMODE0_ENABLE_EMER_THROTTLE bit in MCSMODE0 +/// +fapi2::ReturnCode disable_emergency_throttle (const fapi2::Target& i_target); +/// +/// @brief Perform initializations of the MC translation +/// @tparam P the fapi2::TargetType of the port +/// @tparam TT the mcTraits associated with P +/// @param[in] i_target the target which has the MCA to map +/// @return FAPI2_RC_SUCCESS iff ok +/// +template< fapi2::TargetType P, typename TT = mcTraits

> +fapi2::ReturnCode setup_xlate_map(const fapi2::Target

& i_target); +} //mc +} //mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index 0b869a79b..2cddbadcf 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -47,20 +47,20 @@ using fapi2::TARGET_TYPE_DIMM; using fapi2::FAPI2_RC_SUCCESS; - namespace mss { +namespace mc +{ + -/// /// @brief Perform initializations of the MC translation -/// @tparm P, the fapi2::TargetType of the port -/// @tparm TT, the typename of the traits +/// @tparm P the fapi2::TargetType of the port +/// @tparm TT the typename of the traits /// @param[in] i_target, the target which has the MCA to map /// @return FAPI2_RC_SUCCESS iff ok -/// -template<> + template<> -fapi2::ReturnCode mc::setup_xlate_map(const fapi2::Target& i_target) +fapi2::ReturnCode setup_xlate_map(const fapi2::Target& i_target) { fapi2::buffer l_xlate; fapi2::buffer l_xlate1; @@ -169,7 +169,6 @@ fapi2::ReturnCode mc::setup_xlate_map(const fapi2::Target(0b01101); @@ -212,6 +211,5 @@ fapi2::ReturnCode mc::setup_xlate_map(const fapi2::Target(), o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_SLOT: 0x%lx (system target)", - uint64_t(fapi2::current_err)); - return fapi2::current_err; -} - /// /// @brief ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT getter /// @param[out] uint32_t& reference to store the value diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/find.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/find.H index b549291e1..1b4bca6c5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/find.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/find.H @@ -105,7 +105,7 @@ inline std::vector< fapi2::Target > find_targets( const std::vector< fapi2::Target > l_dimms; // At this time, fapi2 (cronus?) doesn't seem to recognize a DIMM is the child of an MCS. - for (auto p : i_target.getChildren()) + for (const auto& p : i_target.getChildren()) { auto l_these_dimms( p.getChildren() ); l_dimms.insert(l_dimms.end(), l_these_dimms.begin(), l_these_dimms.end()); @@ -120,12 +120,12 @@ inline std::vector< fapi2::Target > find_targets( const /// @return a vector of fapi2::TARGET_TYPE_DIMM /// template<> -inline std::vector< fapi2::Target > find_targets( const - fapi2::Target& i_target ) +inline std::vector< fapi2::Target > find_targets +( const fapi2::Target& i_target ) { std::vector< fapi2::Target > l_dimms; - for (auto p : i_target.getChildren()) + for (const auto& p : i_target.getChildren()) { auto l_these_dimms( p.getChildren() ); l_dimms.insert(l_dimms.end(), l_these_dimms.begin(), l_these_dimms.end()); @@ -141,13 +141,13 @@ inline std::vector< fapi2::Target > find_targets( const /// @note Cronus should support MCS children of an MCBIST - so this might be temporary /// template<> -inline std::vector< fapi2::Target > find_targets( const - fapi2::Target& i_target ) +inline std::vector< fapi2::Target > find_targets +( const fapi2::Target& i_target ) { std::vector< fapi2::Target > l_mcses; // At this time, fapi2 (cronus?) doesn't seem to recognize a MCS is the child of an MCBIST - for (auto p : i_target.getChildren()) + for (const auto& p : i_target.getChildren()) { fapi2::Target l_mcs = p.getParent(); @@ -170,11 +170,34 @@ inline std::vector< fapi2::Target > find_targets( const /// @return a vector of fapi2::TARGET_TYPE_MCA /// template<> -inline std::vector< fapi2::Target > find_targets( const - fapi2::Target& i_target ) +inline std::vector< fapi2::Target > find_targets +( const fapi2::Target& i_target ) { return i_target.getChildren(); } +/// +/// @brief find all the MCA connected to an MCS +/// @param[in] i_target a fapi2::Target MCS +/// @return a vector of fapi2::TARGET_TYPE_MCA +/// +template<> +inline std::vector< fapi2::Target > find_targets +( const fapi2::Target& i_target ) +{ + return i_target.getChildren(); +} + +/// +/// @brief find the MCS given a MCA +/// @param[in] i_target the fapi2 target MCA +/// @return a MCS target. +/// +template<> +inline fapi2::Target find_target( const fapi2::Target& i_target) +{ + return i_target.getParent(); +} + /// /// @brief find all the DIMM connected to an MCA @@ -182,8 +205,8 @@ inline std::vector< fapi2::Target > find_targets( const /// @return a vector of fapi2::TARGET_TYPE_DIMM /// template<> -inline std::vector< fapi2::Target > find_targets( const - fapi2::Target& i_target ) +inline std::vector< fapi2::Target > find_targets +( const fapi2::Target& i_target ) { return i_target.getChildren(); } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index d9ea25caf..be91a7152 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -51,15 +51,13 @@ extern "C" // No need to check to see if we have ports - this loop will just be skipped for (const auto& p : i_target.getChildren()) { - mss::mc l_mc; - // Don't do this yet - leverage the sim inits for the moment #if 0 // All the scominit for this MCA l_mc.scominit(p); #endif // Setup the MC port/dimm address translation registers - FAPI_TRY( l_mc.setup_xlate_map(p) ); + FAPI_TRY( mss::mc::setup_xlate_map(p) ); // Setup the read_pointer_delay // TK: Do we need to do this in general or is this a place holder until the diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C index 54571201a..67f61947c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C @@ -99,3 +99,4 @@ fapi_try_exit: FAPI_INF("End MSS SCOM init"); return fapi2::current_err; } + diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C index cdb187ab0..9d6c06af7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C @@ -21,17 +21,19 @@ /// @file p9_mss_thermal_init.C /// @brief configure and start the OCC and thermal cache /// -// *HWP HWP Owner: Andre Marin +// *HWP HWP Owner: Jacob Harvey // *HWP HWP Backup: Brian Silver // *HWP Team: Memory // *HWP Level: 1 // *HWP Consumed by: FSP:HB #include +#include +#include #include using fapi2::TARGET_TYPE_MCS; - +using fapi2::TARGET_TYPE_MCA; extern "C" { @@ -43,7 +45,15 @@ extern "C" fapi2::ReturnCode p9_mss_thermal_init( const fapi2::Target& i_target ) { FAPI_INF("Start thermal_init"); + + for (const auto& p : mss::find_targets(i_target)) + { + FAPI_TRY(mss::mc::thermal_throttle_scominit(p)); + } + + FAPI_TRY (mss::mc::disable_emergency_throttle(i_target)); FAPI_INF("End thermal_init"); - return fapi2::FAPI2_RC_SUCCESS; + fapi_try_exit: + return fapi2::current_err; } -} +} //extern C diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H index 157badcb7..2abebde11 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.H @@ -38,10 +38,9 @@ extern "C" { /// /// @brief configure and start the OCC and thermal cache -/// @param[in] i_target the controller target +/// @param[in] i_target the controller target (MCS) /// @return FAPI2_RC_SUCCESS iff ok /// fapi2::ReturnCode p9_mss_thermal_init( const fapi2::Target& i_target ); } - #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.mk b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.mk index 66b9a123a..8d472195b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.mk +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.mk @@ -7,7 +7,7 @@ # # EKB Project # -# COPYRIGHT 2015 +# COPYRIGHT 2015,2016 # [+] International Business Machines Corp. # # @@ -16,6 +16,8 @@ # deposited with the U.S. Copyright Office. # # IBM_PROLOG_END_TAG +-include 00common.mk PROCEDURE=p9_mss_thermal_init +$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) -- cgit v1.2.1