From d33402a184c0f6ce2691eff8b862dc90af398f64 Mon Sep 17 00:00:00 2001 From: Jacob Harvey Date: Tue, 7 Mar 2017 11:43:00 -0600 Subject: Change accesses to IS_SIM to use mss accessor Change-Id: Ibadcd2d0ca7daa77705067e69f3aee042492636d Original-Change-Id: Iafcaddbca510c29fb4a0289490b90b539dde2b13 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37610 Reviewed-by: Brian R. Silver Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38014 Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Reviewed-by: Christian R. Geddes --- src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C | 16 ++++++++-------- .../chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index 0703fd828..4f5b2ad6b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -85,8 +85,8 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target l_data; // Don't enable zcal in sim as we don't enable it in the PHY - l_data.writeBit(is_sim ? 0 : 1); + l_data.writeBit(l_sim ? 0 : 1); l_data.insertFromRight(0b01); l_data.insertFromRight(0b010000000); @@ -162,7 +162,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target(is_sim ? 0 : 1); + l_periodic_cal_config.writeBit(l_sim ? 0 : 1); // Write the ZQCAL timer reload register // # DPHY01_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0 0x00A 0x8000c0090301143f @@ -180,7 +180,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target l_zcal_timer_reload; l_zcal_timer_reload.insertFromRight( - is_sim ? (l_zqcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_zqcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1); + l_sim ? (l_zqcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_zqcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1); FAPI_INF("zcal timer reload: 0x%016lx", l_zcal_timer_reload); FAPI_TRY( mss::putScom(i_target, TT::PHY_ZCAL_TIMER_RELOAD_REG, l_zcal_timer_reload) ); } @@ -251,7 +251,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target= 2... // # 0:47 , 0x000000000000, any ;# reserved - // # 48:63 , 0x0000, (def_is_sim) ;# match dials + // # 48:63 , 0x0000, (def_l_sim) ;# match dials // 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/196605)+1), (def_FAST_SIM_PC==0) ;# FAST_SIM_PER_CNTR=0 // 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/765)+1), (def_FAST_SIM_PC==1) ;# FAST_SIM_PER_CNTR=1 // # 48:63 , 0x01D1, any ; # 464 = 114ms @ 1600MHz @@ -263,7 +263,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target(is_sim); + l_periodic_cal_config.writeBit(l_sim); l_periodic_cal_config.writeBit( l_per_memcal_mode_options.getBit() ); @@ -292,7 +292,7 @@ fapi2::ReturnCode enable_periodic_cal( const fapi2::Target l_cal_timer_reload; l_cal_timer_reload.insertFromRight( - is_sim ? (l_memcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_memcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1); + l_sim ? (l_memcal_interval / TT::MAGIC_NUMBER_SIM) + 1 : (l_memcal_interval / TT::MAGIC_NUMBER_NOT_SIM) + 1); FAPI_INF("phy cal timer reload: 0x%016lx", l_cal_timer_reload); FAPI_TRY( mss::putScom(i_target, TT::PHY_CAL_TIMER_RELOAD_REG, l_cal_timer_reload ) ); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H index 390cb1012..e2566c111 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/write_cntrl.H @@ -321,8 +321,8 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits& i_target ) { fapi2::buffer l_data; - uint8_t l_is_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), l_is_sim) ); + uint8_t l_l_sim = 0; + FAPI_TRY( mss::is_simulation(l_l_sim) ); // This is a simplification - in sim we don't have DQS wire delays so we don't acccount for them BRS l_data.insertFromRight(mss::twlo_twloe(i_target)); @@ -331,10 +331,10 @@ inline fapi2::ReturnCode reset_config0( const fapi2::Target& i_target ) l_data.setBit(); // FW_WR_RD [same formula as RD_WR? max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)] - // 57:62, 0b000000, (def_is_sim); # is this max? + // 57:62, 0b000000, (def_l_sim); # is this max? // 57:62, 0b100000, any; # dd0 = 17 clocks, now 32 from SWyatt { - const uint64_t FW_WR_RD = l_is_sim ? 0b000000 : 0b100000; + const uint64_t FW_WR_RD = l_l_sim ? 0b000000 : 0b100000; l_data.insertFromRight(FW_WR_RD); } @@ -410,15 +410,15 @@ template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = wcTraits& i_target ) { fapi2::buffer l_data; - uint8_t l_is_sim = 0; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), l_is_sim) ); + uint8_t l_l_sim = 0; + FAPI_TRY( mss::is_simulation(l_l_sim) ); // MCA_DDRPHY_WC_CONFIG3_P0_MRS_CMD_DQ_ON is 0's - // 55:60, 0b000000, (def_is_sim); # MRS_CMD_DQ_OFF !! + // 55:60, 0b000000, (def_l_sim); # MRS_CMD_DQ_OFF !! // 55:60, 0b111111, any ; # MRS_CMD_DQ_OFF !! { - const uint64_t CMD_DQ_OFF = l_is_sim ? 0b000000 : 0b111111; + const uint64_t CMD_DQ_OFF = l_l_sim ? 0b000000 : 0b111111; l_data.insertFromRight(CMD_DQ_OFF); } -- cgit v1.2.1