From d27c5e1fe4313a349fa16a557299c6d0721cdbce Mon Sep 17 00:00:00 2001 From: Ben Gass Date: Wed, 6 Mar 2019 17:25:00 -0500 Subject: Update ATRMISS registers for Axone The address changed and there are now two. Change-Id: Iad60f8ec843ed61d28ef11903d8258ecfe213aa3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72965 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Reviewed-by: Benjamin Gass Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72986 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../chips/p9/procedures/hwp/nest/p9_npu_scominit.C | 45 ++++++++++++++++------ 1 file changed, 34 insertions(+), 11 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp') diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C index b82040e89..cf3edc4f4 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,6 +40,8 @@ #include #include #include +#include +#include //------------------------------------------------------------------------------ // Constant definitions @@ -70,6 +72,7 @@ fapi2::ReturnCode p9_npu_scominit( fapi2::ReturnCode l_rc; fapi2::buffer l_atrmiss = 0; fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR_Type l_npu_p9n_dd1; + fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR_Type l_axone; // read attribute to determine if P9N DD1 NPU addresses should be used FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR, @@ -77,6 +80,11 @@ fapi2::ReturnCode p9_npu_scominit( l_npu_p9n_dd1), "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR, + i_target, + l_axone), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_AXONE_ADDR)"); + // apply NPU SCOM inits from initfile FAPI_DBG("Invoking p9.npu.scom.initfile..."); FAPI_EXEC_HWP(l_rc, @@ -95,16 +103,31 @@ fapi2::ReturnCode p9_npu_scominit( l_atrmiss.setBit() .setBit(); - FAPI_TRY(fapi2::putScomUnderMask(i_target, - ((l_npu_p9n_dd1) ? - (PU_NPU_SM2_XTS_ATRMISS) : - (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)), - l_atrmiss, - l_atrmiss), - "Error from putScomUnderMask (0x%08X)", - ((l_npu_p9n_dd1) ? - (PU_NPU_SM2_XTS_ATRMISS) : - (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1))); + if (!l_axone) + { + FAPI_TRY(fapi2::putScomUnderMask(i_target, + ((l_npu_p9n_dd1) ? + (PU_NPU_SM2_XTS_ATRMISS) : + (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1)), + l_atrmiss, + l_atrmiss), + "Error from putScomUnderMask (0x%08X)", + ((l_npu_p9n_dd1) ? + (PU_NPU_SM2_XTS_ATRMISS) : + (PU_NPU_SM2_XTS_ATRMISS_POST_P9NDD1))); + } + else + { + // Axone + // P9A_PU_NPU2_NTL1_XTS_ATRMISS = 0x050112FA + FAPI_TRY(fapi2::putScomUnderMask(i_target, P9A_PU_NPU2_NTL1_XTS_ATRMISS, l_atrmiss, l_atrmiss), + "Error from putScomUnderMask (0x%08X)", + P9A_PU_NPU2_NTL1_XTS_ATRMISS); + // P9A__NTL1_XTS_ATRMISS = 0x050116FA + FAPI_TRY(fapi2::putScomUnderMask(i_target, P9A__NTL1_XTS_ATRMISS, l_atrmiss, l_atrmiss), + "Error from putScomUnderMask (0x%08X)", + P9A__NTL1_XTS_ATRMISS); + } // enable NVLINK refclocks FAPI_DBG("Invoking p9_nv_ref_clk_enable..."); -- cgit v1.2.1