From c0fce11639f72a479e3479a25362cf64337e51a1 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Wed, 7 Feb 2018 16:37:55 -0600 Subject: enforce strict 512 GB per socket limit on Witherspoon memory map (part2) first commit merged before HW testing was complete, and caused issue with skiboot's detection of the MCD workaround mechanism this update restores the chip address extension HW programming to 0x7, (to avoid a coreq skiboot change) but should still restrict the allocation to lie within the first 512 GB of address space on each socket Change-Id: Ie844a609c16ffa1aa38091bae42145da9c7912a4 CQ: SW415901 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53594 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: FSP CI Jenkins Reviewed-by: Thi N. Tran Reviewed-by: Jenny Huynh Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53641 CI-Ready: Daniel M. Crowell Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C | 5 ++++- src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H | 4 ++-- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp') diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C index b702525ba..ae5729331 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -295,6 +295,9 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( l_addr_extension_chip_id), "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID"); + // mask all but LSB, prevent regions above RA bit 21 from being exposed to callers + l_addr_extension_chip_id &= 0x01; + // align to RA l_addr_extension_enable.insertFromRight < FABRIC_ADDR_LS_GROUP_ID_START_BIT, FABRIC_ADDR_LS_GROUP_ID_END_BIT - FABRIC_ADDR_LS_GROUP_ID_START_BIT + 1 > diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H index 419c8df11..28be4dfea 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -70,9 +70,9 @@ const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL; const uint64_t FABRIC_CACHELINE_SIZE = 0x80; // chip address extension mask, for HW423589_OPTION2 -// repurposes chip ID(2) as address bits +// repurposes chip ID(0:2) as address bits const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2 = 0x0; -const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x1; +const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x7; const uint64_t MAX_INTERLEAVE_GROUP_SIZE = 0x40000000000ULL; // 4_TB const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL; // 512_GB -- cgit v1.2.1