From 2209292ea1a7f54bfa0c5452fb9039b38d5a1985 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Wed, 18 Oct 2017 13:41:51 -0500 Subject: Chip address extension workaround for HW423589 (option2), part1 chip_ec_attributes.xml nest_attributes.xml p9_sbe_attributes.xml add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines set of chips which physically support the feature add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips which need extended address workaround for MCD issue (applied only to Nimbus EC 21) add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of memory groups formed. Written by p9_mss_eff_grouping. For HW423589_OPTION2, this will default to 512GB add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold extended address configuration. Written by p9_sbe_fabricinit (SBE) and p9_mss_eff_grouping (HB). For HW423589_OPTION2, this will default to 0b0000_111, consuming all chip ID bits for extended addressing. p9_fbc_utils.C p9_fbc_utils.H extend p9_fbc_utils_get_chip_base_address to support address extension, now outputs set of ranges in each msel based on ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID maintain original function for PPE platform which requires knowledge of non-aliased base addresses only, for code size p9_mss_eff_grouping.C p9_mss_eff_grouping_errors.xml set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform restrict size of groups formed for HW423589_OPTION2 p9_sbe_fabricinit.C set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform configure FBC/NMMU extended addressing registers p9_setup_bars.C p9_setup_bars_defs.H p9_setup_bars_errors.xml add general purpose support for extended address mode for HW423589_OPTION2, configure static MCD setup p9_hcode_image_defines.H p9_hcode_image_build.C customize SGPE image with address extension configuration to apply p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scom.initfile p9.l3.scom.initfile p9.ncu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_hcd_cache_scominit.C p9_hcd_cache_scominit.c p9_pcie_config.C set unit address extension configuration on supported chips p9_rng_init_phase2.C p9_sbe_scominit.C p9c_set_inband_addr.C p9_sbe_load_bootloader.C p9_sbe_mcs_setup.C adapt to alterations in p9_fbc_utils_get_chip_base_address Change-Id: I614d566c073f1169f04f647057e6e85889f1c237 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576 Reviewed-by: Joseph J. McGill Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Tested-by: FSP CI Jenkins Reviewed-by: Gregory S. Still Tested-by: PPE CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48893 Reviewed-by: Hostboot Team Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell --- .../p9/procedures/hwp/initfiles/p9_cxa_scom.C | 11 ++ .../p9/procedures/hwp/initfiles/p9_int_scom.C | 11 ++ .../chips/p9/procedures/hwp/initfiles/p9_nx_scom.C | 11 ++ .../p9/procedures/hwp/initfiles/p9_vas_scom.C | 18 ++- .../p9/procedures/hwp/lib/p9_hcode_image_defines.H | 2 +- .../chips/p9/procedures/hwp/nest/p9_fbc_utils.C | 128 ++++++++++++++++++++- .../chips/p9/procedures/hwp/nest/p9_fbc_utils.H | 49 +++++++- .../p9/procedures/hwp/nest/p9_mss_eff_grouping.C | 16 +-- .../chips/p9/procedures/hwp/nest/p9_pcie_config.C | 37 +++++- .../p9/procedures/hwp/nest/p9_rng_init_phase2.C | 4 +- .../chips/p9/procedures/hwp/nest/p9_setup_bars.C | 4 +- .../p9/procedures/hwp/nest/p9c_set_inband_addr.C | 5 +- .../p9/procedures/hwp/pm/p9_hcode_image_build.C | 44 ++++++- 13 files changed, 303 insertions(+), 37 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp') diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C index 7fdd9a937..a5bc32cad 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_cxa_scom.C @@ -52,6 +52,10 @@ fapi2::ReturnCode p9_cxa_scom(const fapi2::Target& TGT0 FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW414700)); fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)); fapi2::buffer l_scom_buffer; { FAPI_TRY(fapi2::getScom( TGT0, 0x2010803ull, l_scom_buffer )); @@ -122,6 +126,13 @@ fapi2::ReturnCode p9_cxa_scom(const fapi2::Target& TGT0 l_scom_buffer.insert<6, 1, 63, uint64_t>(l_CAPP0_CXA_TOP_CXA_APC0_APCCTL_SKIP_G_OFF ); } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) ) + { + l_scom_buffer.insert<21, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID ); + l_scom_buffer.insert<25, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x2010818ull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C index cc14cb9b9..94af9fd2b 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_int_scom.C @@ -64,6 +64,10 @@ fapi2::ReturnCode p9_int_scom(const fapi2::Target& FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec)); fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)); fapi2::ATTR_CHIP_EC_FEATURE_HW411637_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW411637; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW411637, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW411637)); fapi2::ATTR_CHIP_EC_FEATURE_P9N_INT_DD10_Type l_TGT0_ATTR_CHIP_EC_FEATURE_P9N_INT_DD10; @@ -85,6 +89,13 @@ fapi2::ReturnCode p9_int_scom(const fapi2::Target& l_scom_buffer.insert<1, 1, 63, uint64_t>(literal_0 ); } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) ) + { + l_scom_buffer.insert<5, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID ); + l_scom_buffer.insert<9, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x501300aull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C index d943dbb07..b486e2090 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_nx_scom.C @@ -57,6 +57,10 @@ fapi2::ReturnCode p9_nx_scom(const fapi2::Target& FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW414700)); fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)); fapi2::buffer l_scom_buffer; { FAPI_TRY(fapi2::getScom( TGT0, 0x2011041ull, l_scom_buffer )); @@ -652,6 +656,13 @@ fapi2::ReturnCode p9_nx_scom(const fapi2::Target& l_scom_buffer.insert<24, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_SKIP_G_OFF ); } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) ) + { + l_scom_buffer.insert<56, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID ); + l_scom_buffer.insert<60, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID ); + } + constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_RD_GO_M_QOS_ON = 0x1; l_scom_buffer.insert<22, 1, 63, uint64_t>(l_NX_PBI_CQ_WRAP_NXCQ_SCOM_RD_GO_M_QOS_ON ); constexpr auto l_NX_PBI_CQ_WRAP_NXCQ_SCOM_ADDR_BAR_MODE_OFF = 0x0; diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C index e4408a843..193d6d1bf 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_vas_scom.C @@ -48,6 +48,10 @@ fapi2::ReturnCode p9_vas_scom(const fapi2::Target& FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec)); fapi2::ATTR_CHIP_EC_FEATURE_HW414700_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW414700; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW414700)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)); fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE)); fapi2::buffer l_scom_buffer; @@ -114,13 +118,21 @@ fapi2::ReturnCode p9_vas_scom(const fapi2::Target& } } { - if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) + FAPI_TRY(fapi2::getScom( TGT0, 0x301184dull, l_scom_buffer )); + + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) ) { - FAPI_TRY(fapi2::getScom( TGT0, 0x301184dull, l_scom_buffer )); + l_scom_buffer.insert<0, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID ); + l_scom_buffer.insert<4, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID ); + } + if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) + { l_scom_buffer.insert<19, 1, 63, uint64_t>(literal_0x1 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x301184dull, l_scom_buffer)); } + + FAPI_TRY(fapi2::putScom(TGT0, 0x301184dull, l_scom_buffer)); } { FAPI_TRY(fapi2::getScom( TGT0, 0x301184eull, l_scom_buffer )); diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index c1a7eee54..e9df4d592 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -236,7 +236,7 @@ HCD_HDR_UINT32(g_sgpe_build_date, 0); HCD_HDR_UINT32(g_sgpe_build_ver, 0); HCD_HDR_UINT32(g_sgpe_reserve_flags, 0); HCD_HDR_UINT16(g_sgpe_location_id, 0); -HCD_HDR_UINT16(g_sgpe_reserve3, 0); +HCD_HDR_UINT16(g_sgpe_addr_extension, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_cmn_ring_ovrd_occ_offset, 0); HCD_HDR_UINT32(g_sgpe_spec_ring_occ_offset, 0); diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C index 0d26866b8..6faa9705f 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C @@ -145,7 +145,7 @@ fapi_try_exit: // NOTE: see comments above function prototype in header -fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases( const fapi2::Target& i_target, const p9_fbc_utils_addr_mode_t i_addr_mode, uint64_t& o_base_address_nm0, @@ -198,7 +198,6 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( } // else, leave chip ID=0 for the purposes of establishing drawer base address - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, l_mirror_policy), "Error from FAPI_ATTR_GET (ATTR_MEM_MIRROR_PLACEMENT_POLICY)"); @@ -245,3 +244,128 @@ fapi_try_exit: FAPI_DBG("End"); return fapi2::current_err; } + + +// NOTE: see comments above function prototype in header +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( + const fapi2::Target& i_target, + const p9_fbc_utils_addr_mode_t i_addr_mode, + std::vector& o_base_address_nm0, + std::vector& o_base_address_nm1, + std::vector& o_base_address_m, + uint64_t& o_base_address_mmio) +{ + uint64_t l_base_address_nm0 = 0; + uint64_t l_base_address_nm1 = 0; + uint64_t l_base_address_m = 0; + uint8_t l_addr_extension_group_id; + uint8_t l_addr_extension_chip_id; + fapi2::buffer l_addr_extension_enable = 0; + uint8_t l_regions_per_msel = 1; + std::vector l_alias_bit_positions; + fapi2::Target FAPI_SYSTEM; + + fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode; + fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2_Type l_hw423589_option2; + + FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target, + i_addr_mode, + l_base_address_nm0, + l_base_address_nm1, + l_base_address_m, + o_base_address_mmio), + "Error from p9_fbc_utils_get_chip_base_address_no_aliases"); + + // read attributes defining address extension enable configuration + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, i_target, l_extended_addressing_mode), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, i_target, l_hw423589_option2), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW423589_OPTION2)"); + + if (l_extended_addressing_mode) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, + FAPI_SYSTEM, + l_addr_extension_group_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, + FAPI_SYSTEM, + l_addr_extension_chip_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID"); + + // align to RA + l_addr_extension_enable.insertFromRight < FABRIC_ADDR_LS_GROUP_ID_START_BIT, + FABRIC_ADDR_LS_GROUP_ID_END_BIT - FABRIC_ADDR_LS_GROUP_ID_START_BIT + 1 > + (l_addr_extension_group_id); + l_addr_extension_enable.insertFromRight < FABRIC_ADDR_LS_CHIP_ID_START_BIT, + FABRIC_ADDR_LS_CHIP_ID_END_BIT - FABRIC_ADDR_LS_CHIP_ID_START_BIT + 1 > + (l_addr_extension_chip_id); + } + + // walk across bits set in enable bit field, count number of bits set + // to determine permutations + FAPI_DBG("Address extension enable mask: 0x%016lX", l_addr_extension_enable()); + + if (l_addr_extension_enable != 0) + { + for (uint8_t ii = FABRIC_ADDR_LS_GROUP_ID_START_BIT; + ii <= FABRIC_ADDR_LS_CHIP_ID_END_BIT; + ii++) + { + if (l_addr_extension_enable.getBit(ii)) + { + l_regions_per_msel *= 2; + l_alias_bit_positions.push_back(ii); + } + } + } + + FAPI_DBG("Valid regions per msel: %d", l_regions_per_msel); + + for (uint8_t l_region = 0; + l_region < l_regions_per_msel; + l_region++) + { + fapi2::buffer l_alias_mask = 0; + FAPI_DBG("Generating region: %d", l_region); + + if (l_region) + { + uint8_t l_value = l_region; + + for (int jj = l_alias_bit_positions.size() - 1; + jj >= 0; + jj--) + { + l_alias_mask.writeBit(l_value & 1, + l_alias_bit_positions[jj]); + l_value = l_value >> 1; + } + } + + FAPI_DBG("Mask: 0x%016lX", l_alias_mask()); + + // hide region reserved for GPU LPC + if (!l_hw423589_option2 || (l_region != 1)) + { + o_base_address_nm0.push_back(l_base_address_nm0 | + l_alias_mask()); + o_base_address_m.push_back(l_base_address_m | + l_alias_mask()); + } + + // second non-mirrored msel region unusable with HW423589_OPTION2 + // (no MCD resources available to map) + if (!l_hw423589_option2) + { + o_base_address_nm1.push_back(l_base_address_nm1 | + l_alias_mask()); + } + } + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H index 7d9cefa67..b59807103 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -69,6 +69,13 @@ const uint64_t P9_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL; // cacheline size = 128B const uint64_t FABRIC_CACHELINE_SIZE = 0x80; +// chip address extension mask, for HW423589_OPTION2 +// repurposes chip ID(0:2) as address bits +const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_HW423589_OPTION2 = 0x0; +const uint8_t CHIP_ADDRESS_EXTENSION_CHIP_ID_MASK_HW423589_OPTION2 = 0x7; + +const uint64_t MAX_INTERLEAVE_GROUP_SIZE = 0x40000000000ULL; // 4_TB +const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL; // 512_GB //------------------------------------------------------------------------------ // Function prototypes @@ -99,17 +106,22 @@ fapi2::ReturnCode p9_fbc_utils_override_fbc_stop( const fapi2::Target& i_target); /// -/// @brief Return base address origin (non-mirrored/mirrored/MMIO) for this chip +/// @brief Return set of base addresses (non-mirrored/mirrored/MMIO) for this chip, +/// accounting for fixed msel assignments, but not aliasing +/// enabled by chip address extension facility /// /// @param[in] i_target Reference to processor chip target /// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations -/// @param[out] o_base_address_nm0 Non-mirrored base address (range 0) for this chip -/// @param[out] o_base_address_nm1 Non-mirrored base address (range 1) for this chip -/// @param[out] o_base_address_m Mirrored base address for this chip -/// @param[out] o_base_address_mmio MMIO base address for this chip +/// @param[out] o_base_address_nm0 Non-mirrored base address for +/// this chip (covering msel=0b00) +/// @param[out] o_base_address_nm1 Non-mirrored base address for +/// this chip (covering msel=0b01) +/// @param[out] o_base_address_m Mirrored base address for +/// this chip (covering msel=0b10) +/// @param[out] o_base_address_mmio MMIO base address for this chip (msel=0b11) /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. /// -fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address_no_aliases( const fapi2::Target& i_target, const p9_fbc_utils_addr_mode_t i_addr_mode, uint64_t& o_base_address_nm0, @@ -117,4 +129,29 @@ fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( uint64_t& o_base_address_m, uint64_t& o_base_address_mmio); +/// +/// @brief Return set of base addresses (non-mirrored/mirrored/MMIO) for this chip, +/// accounting for fixed msel assignments as well as variable aliasing +/// enabled by chip address extension facility +/// +/// @param[in] i_target Reference to processor chip target +/// @param[in] i_addr_mode Specifies mode for chip base/origin address calculations +/// @param[out] o_base_address_nm0 List of non-mirrored base addresses for +/// this chip (covering msel=0b00), ordered from smallest->largest +/// @param[out] o_base_address_nm1 List of non-mirrored base addresses for +/// this chip (covering msel=0b01), ordered from smallest->largest +/// @param[out] o_base_address_m List of mirrored base addresses for +/// this chip (covering msel=0b10), ordered from +/// smallest->largest +/// @param[out] o_base_address_mmio MMIO base address for this chip (msel=0b11) +/// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( + const fapi2::Target& i_target, + const p9_fbc_utils_addr_mode_t i_addr_mode, + std::vector& o_base_address_nm0, + std::vector& o_base_address_nm1, + std::vector& o_base_address_m, + uint64_t& o_base_address_mmio); + #endif // _P9_FBC_UTILS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C index 434da9f32..aa6bd504e 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C @@ -212,25 +212,13 @@ fapi2::ReturnCode EffGroupingProcAttrs::calcProcBaseAddr( uint64_t l_memBaseAddr1, l_mmioBaseAddr; // Get the Mirror/Non-mirror base addresses - FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, + FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target, EFF_FBC_GRP_CHIP_IDS, iv_memBaseAddr, l_memBaseAddr1, iv_mirrorBaseAddr, l_mmioBaseAddr), - "p9_fbc_utils_get_chip_base_address() returns an error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); - - // Write base addr for non-mirror memory regions - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_MEM_BASE, i_target, - iv_memBaseAddr), - "Error setting ATTR_PROC_MEM_BASE, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); - - // Set base addr for mirror memory regions - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_MIRROR_BASE, i_target, - iv_mirrorBaseAddr), - "Error setting ATTR_PROC_MIRROR_BASE, l_rc 0x%.8X", + "p9_fbc_utils_get_chip_base_address_no_aliases() returns an error, l_rc 0x%.8X", (uint64_t)fapi2::current_err); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C index 95d9ace99..9026870ba 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C @@ -41,7 +41,9 @@ #include #include - +#include +#include +#include //------------------------------------------------------------------------------ // Constant definitions @@ -86,11 +88,13 @@ fapi2::ReturnCode p9_pcie_config( fapi2::ATTR_PROC_PCIE_BAR_SIZE_Type l_bar_sizes; fapi2::ATTR_CHIP_EC_FEATURE_HW363246_Type l_hw363246; fapi2::ATTR_CHIP_EC_FEATURE_HW410503_Type l_hw410503; + fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode; fapi2::Target FAPI_SYSTEM; fapi2::buffer l_buf = 0; uint8_t l_attr_proc_pcie_iovalid_enable = 0; - uint64_t l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m, l_base_addr_mmio; + std::vector l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m; + uint64_t l_base_addr_mmio; auto l_pec_chiplets_vec = i_target.getChildren( fapi2::TARGET_STATE_FUNCTIONAL); @@ -138,6 +142,11 @@ fapi2::ReturnCode p9_pcie_config( l_hw363246), "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_HW363246)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, + i_target, + l_extended_addressing_mode), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)"); + // initialize functional PEC chiplets for (auto l_pec_chiplet : l_pec_chiplets_vec) { @@ -153,6 +162,30 @@ fapi2::ReturnCode p9_pcie_config( l_attr_proc_pcie_iovalid_enable)); FAPI_DBG("l_attr_proc_pcie_iovalid_enable: %#x", l_attr_proc_pcie_iovalid_enable); + // configure extended addressing facility + if (l_extended_addressing_mode) + { + uint8_t l_addr_extension_group_id; + uint8_t l_addr_extension_chip_id; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, + FAPI_SYSTEM, + l_addr_extension_group_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, + FAPI_SYSTEM, + l_addr_extension_chip_id), + "Error from FAPI_ATTR_GET (ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)"); + + FAPI_TRY(fapi2::getScom(l_pec_chiplet, P9N2_PEC_ADDREXTMASK_REG, l_buf), + "Error from getScom (P9N2_PEC_ADDREXTMASK_REG)"); + l_buf.insertFromRight( + (l_addr_extension_group_id << 3) | + l_addr_extension_chip_id); + FAPI_TRY(fapi2::putScom(l_pec_chiplet, P9N2_PEC_ADDREXTMASK_REG, l_buf), + "Error from putScom (P9N2_PEC_ADDREXTMASK_REG)"); + } + // Phase2 init step 1 // NestBase+0x00 // Set bits 00:03 = 0b0001 Set hang poll scale diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C index e265fc969..7c7017396 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_rng_init_phase2.C @@ -67,9 +67,7 @@ p9_rng_init_phase2(const fapi2::Target& i_target) uint64_t l_nx_rng_bar_base_addr_offset = 0; uint8_t l_nx_rng_failed_int_enable = 0; uint64_t l_nx_rng_failed_int_addr = 0; - uint64_t l_base_addr_nm0; - uint64_t l_base_addr_nm1; - uint64_t l_base_addr_m; + std::vector l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m; uint64_t l_base_addr_mmio; uint8_t l_HW403701; diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C index 54e201fc8..7223b2098 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C @@ -69,13 +69,13 @@ p9_setup_bars_build_chip_info(const fapi2::Target& { FAPI_DBG("Start"); - FAPI_TRY(p9_fbc_utils_get_chip_base_address(i_target, + FAPI_TRY(p9_fbc_utils_get_chip_base_address_no_aliases(i_target, EFF_FBC_GRP_CHIP_IDS, io_chip_info.base_address_nm[0], io_chip_info.base_address_nm[1], io_chip_info.base_address_m, io_chip_info.base_address_mmio), - "Error from p9_fbc_utils_get_chip_base_address"); + "Error from p9_fbc_utils_get_chip_base_address_no_aliases"); FAPI_TRY(p9_fbc_utils_get_group_id_attr(i_target, io_chip_info.fbc_group_id), diff --git a/src/import/chips/p9/procedures/hwp/nest/p9c_set_inband_addr.C b/src/import/chips/p9/procedures/hwp/nest/p9c_set_inband_addr.C index 2e578707c..8dbb825f5 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9c_set_inband_addr.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9c_set_inband_addr.C @@ -50,7 +50,10 @@ fapi2::ReturnCode p9c_set_inband_addr( const fapi2::Target& i_target) { - uint64_t l_base_addr_nm0, l_base_addr_nm1, l_base_addr_m, l_base_addr_mmio; + std::vector l_base_addr_nm0; + std::vector l_base_addr_nm1; + std::vector l_base_addr_m; + uint64_t l_base_addr_mmio; FAPI_DBG("Start"); // determine base address of chip MMIO range diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 717cb5f22..75cd9dcb0 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -3451,11 +3451,17 @@ fapi2::ReturnCode setFabricIds( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i { FAPI_INF(">> setFabricIds"); + const fapi2::Target FAPI_SYSTEM; uint32_t l_system_id; uint8_t l_group_id; uint8_t l_chip_id; + uint8_t l_addr_extension_group_id; + uint8_t l_addr_extension_chip_id; fapi2::buffer l_location_id = 0; + fapi2::buffer l_addr_extension = 0; + fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE_Type l_extended_addressing_mode; uint16_t l_locationVal = 0; + uint16_t l_addr_extension_val = 0; cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; @@ -3502,6 +3508,39 @@ fapi2::ReturnCode setFabricIds( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i // Populate the SGPE Header pSgpeHdr->g_sgpe_location_id = SWIZZLE_2_BYTE(l_locationVal); + // configure extended addressing facility + // only place non zero value in SGPE header if supported by chip type + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, + i_procTgt, + l_extended_addressing_mode), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE)"); + + if (l_extended_addressing_mode) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, + FAPI_SYSTEM, + l_addr_extension_group_id), + "Error from FAPI_ATTR_GET for attribute ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID"); + + FAPI_DBG("Fabric Address Extension Group ID : 0x%01X", l_addr_extension_group_id); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, + FAPI_SYSTEM, + l_addr_extension_chip_id), + "Error from FAPI_ATTR_GET for attribute ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID"); + + FAPI_DBG("Fabric Address Extension Chip ID : 0x%01X", l_addr_extension_chip_id); + + l_addr_extension.insert<0, 4, 8-4, uint8_t>(l_addr_extension_group_id); + l_addr_extension.insert<4, 3, 8-3, uint8_t>(l_addr_extension_chip_id); + } + + FAPI_DBG("Address Extension ID : 0x%04X", l_addr_extension); + l_addr_extension.extract<0, 16>(l_addr_extension_val); + + // Populate the SGPE Header + pSgpeHdr->g_sgpe_addr_extension = SWIZZLE_2_BYTE(l_addr_extension_val); + fapi_try_exit: FAPI_INF("<< setFabricIds"); return fapi2::current_err; @@ -3523,9 +3562,8 @@ fapi2::ReturnCode populateNcuRngBarScomReg( void* i_pChipHomer, CONST_FAPI2_PROC uint8_t attrVal = 0; uint64_t nxRangeBarAddrOffset = 0; uint64_t regNcuRngBarData = 0; - uint64_t baseAddressNm0 = 0; - uint64_t baseAddressNm1 = 0; - uint64_t baseAddressMirror = 0; + std::vector baseAddressNm0, baseAddressNm1; + std::vector baseAddressMirror; uint32_t ncuBarRegisterAddr = 0; const fapi2::Target FAPI_SYSTEM; -- cgit v1.2.1