From 4e919f5e820fee0f61769f2752b0920b040e66d6 Mon Sep 17 00:00:00 2001 From: Greg Still Date: Fri, 18 May 2018 15:45:11 -0500 Subject: PM: clear Hcode error injection bit upon PM complex reset - Clearomh the bits lets STOPs and PStates be restarted during the reset. Injection has to be done after the subsystem is initialized. - Clear the CSAR bits in p9_pm_corequad_init(init) - Clear SGPE and PGPE error inject bits in OCC Flag2 (p9_pm_stop_gpe_init and p9_pm_pstate_gpe_init respectively Key_Cronus_Test=PM_REGRESS Change-Id: I93bfe8d4b0959a6a305722df1e2c518f3dfc08fc CQ:SW429797 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59078 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: Cronus HW CI Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: YUE DU Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59085 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- .../chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C | 16 ++++++++++++++++ .../p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C | 14 +++++++++++++- .../chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C | 20 ++++++++++++-------- 3 files changed, 41 insertions(+), 9 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/pm') diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C index 8579f3df4..47f6f561d 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C @@ -50,6 +50,7 @@ /// Clear CME flags and scratch registers as these will be setup /// via CME booting during SGPE boot /// Clear PPM Errors +/// Clear Hcode Error Injection enable bits /// Restore PPM Error mask value from HWP attribute /// } /// } @@ -91,6 +92,7 @@ #include #include #include +#include #include // ----------------------------------------------------------------------------- @@ -339,6 +341,20 @@ fapi2::ReturnCode pm_corequad_init( FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), "ERROR: Failed to clear CORE PPM ERROR"); + FAPI_INF("Clearing Hcode Error Injection and other CSAR settings ..."); + // *INDENT-OFF* + l_data64.flush<0>() + .setBit() + .setBit() + .setBit() + .setBit(); + // Note: CPPM_CSAR_DISABLE_CME_NACK_ON_PROLONGED_DROOP is NOT + // cleared as this is a persistent, characterization setting + // *INDENT-ON* + l_address = C_CPPM_CSAR_CLEAR; + FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), + "ERROR: Failed to clear the CSAR register"); + // Restore CORE PPM Error Mask FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CORE_PPM_ERRMASK, l_core_chplt, diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C index 59904d7c3..8483b9308 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C @@ -48,7 +48,13 @@ // ----------------------------------------------------------------------------- // Constants // ----------------------------------------------------------------------------- -// @todo RTC 148540 Refine this values for the lab + +// Map the auto generated names to clearer ones +static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1; +static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2; +static const uint64_t PU_OCB_OCI_OCCFLG2_CLEAR = P9N2_PU_OCB_OCI_OCCFLG2_SCOM1; +static const uint64_t PU_OCB_OCI_OCCFLG2_SET = P9N2_PU_OCB_OCI_OCCFLG2_SCOM2; + // Following constants hold an approximate value. static const uint32_t PGPE_TIMEOUT_MS = 500; static const uint32_t PGPE_TIMEOUT_MCYCLES = 20; @@ -157,6 +163,12 @@ fapi2::ReturnCode pstate_gpe_init( .insertFromRight<4, 4>(0xA); // FIT FAPI_TRY(fapi2::putScom(i_target, PU_GPE2_GPETSEL_SCOM, l_data64)); + // Clear error injection bits + l_data64.flush<0>() + .setBit() + .setBit(); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64)); + // Program XCR to ACTIVATE PGPE FAPI_INF(" Starting the PGPE..."); l_xcr.flush<0>().insertFromRight(p9hcd::HARD_RESET, 1, 3); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C index 02ee7c5b9..8c3d84409 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_stop_gpe_init.C @@ -43,6 +43,7 @@ /// - call p9_pm_pba_init in PM_RESET mode to get the PBA in "boot" mode /// - Read the SGPE IVPR value that is in HOMER from Attribute written /// by p9_hcode_image_build +/// - Clear error injection bits /// - Sreset the SGPE to start the boot copier from . /// - Polls OCC Flag bit for HCode init completion /// - Starting the SGPE will cause a "reboot" of functional CMEs @@ -72,16 +73,15 @@ #include #include -//#include @todo RTC 147996 to incorporate PPE state removing strings. - - // ---------------------------------------------------------------------- // Constants // ---------------------------------------------------------------------- // Map the auto generated names to clearer ones -static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1; -static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2; +static const uint64_t PU_OCB_OCI_OCCFLG_CLEAR = PU_OCB_OCI_OCCFLG_SCOM1; +static const uint64_t PU_OCB_OCI_OCCFLG_SET = PU_OCB_OCI_OCCFLG_SCOM2; +static const uint64_t PU_OCB_OCI_OCCFLG2_CLEAR = P9N2_PU_OCB_OCI_OCCFLG2_SCOM1; +static const uint64_t PU_OCB_OCI_OCCFLG2_SET = P9N2_PU_OCB_OCI_OCCFLG2_SCOM2; static const uint32_t SGPE_TIMEOUT_MS = 2500; // Guess at this time static const uint32_t SGPE_TIMEOUT_MCYCLES = 20; // Guess at this time @@ -317,6 +317,10 @@ fapi2::ReturnCode p9_pm_stop_gpe_init( .insertFromRight<4, 4>(0xA); // FIT FAPI_TRY(fapi2::putScom(i_target, PU_GPE3_GPETSEL_SCOM, l_data64)); + // Clear error injection bits + l_data64.flush<0>().setBit(); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64)); + // Set the Malf Alert Enabled policy to OCCFLG2 reg bit 29 FAPI_IMP ("Malf Alert Policy Enabled: %d", malfAlertEnable); @@ -324,11 +328,11 @@ fapi2::ReturnCode p9_pm_stop_gpe_init( if (malfAlertEnable == fapi2::ENUM_ATTR_PM_MALF_ALERT_ENABLE_TRUE) { - FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM2, l_data64)); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_SET, l_data64)); } else { - FAPI_TRY(fapi2::putScom(i_target, P9N2_PU_OCB_OCI_OCCFLG2_SCOM1, l_data64)); + FAPI_TRY(fapi2::putScom(i_target, PU_OCB_OCI_OCCFLG2_CLEAR, l_data64)); } FAPI_IMP ("Malf Alert Policy Set to OCC FLAG2 .. now init SGPE"); @@ -540,7 +544,7 @@ fapi2::ReturnCode stop_gpe_reset( FAPI_INF(" Clear SGPE_ACTIVE in OCC Flag Register..."); l_data64.flush<0>().setBit(); - FAPI_TRY(putScom(i_target, PU_OCB_OCI_OCCFLG_SCOM1, l_data64)); + FAPI_TRY(putScom(i_target, PU_OCB_OCI_OCCFLG_CLEAR, l_data64)); fapi_try_exit: FAPI_IMP("<< stop_gpe_reset..."); -- cgit v1.2.1