From fad02a31a3fe06ffd3ed4e46710018a8c42a3902 Mon Sep 17 00:00:00 2001 From: Ben Gass Date: Wed, 18 May 2016 13:01:57 -0500 Subject: Translate logical mca regisers in mcs chiplet as mca target type Fixup memory code which uses the xlt registers Add dependent epsilon inits Change-Id: I0a41542f758f52081e4e5877df1af65c27755795 Original-Change-Id: I995bcd895a0a7a431dcf350475fd387be70749c9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24733 Reviewed-by: Brian R. Silver Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Dev-Ready: Benjamin Gass Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82425 Reviewed-by: Daniel M Crowell Tested-by: Daniel M Crowell --- .../chips/p9/procedures/hwp/memory/lib/mc/mc.C | 37 ---------------------- 1 file changed, 37 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/memory') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index 66d5dcf75..19308668d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -46,10 +46,6 @@ using fapi2::TARGET_TYPE_MCS; namespace mss { -const uint64_t mcTraits::xlate0_reg[] = {MCS_PORT02_MCP0XLT0, MCS_PORT13_MCP0XLT0}; -const uint64_t mcTraits::xlate1_reg[] = {MCS_PORT02_MCP0XLT1, MCS_PORT13_MCP0XLT1}; -const uint64_t mcTraits::xlate2_reg[] = {MCS_PORT02_MCP0XLT2, MCS_PORT13_MCP0XLT2}; - /// /// @brief Dump the registers of the MC (MCA_MBA, MCS) /// @param[in] i_target the MCS target @@ -132,39 +128,6 @@ fapi2::ReturnCode dump_regs( const fapi2::Target& i_target ) {"MCS_MCSYNC", MCS_MCSYNC }, {"MCS_MCTO", MCS_MCTO }, {"MCS_MCWATCNTL", MCS_MCWATCNTL }, - - {"MCS_PORT02_AACR", MCS_PORT02_AACR }, - {"MCS_PORT02_AADR", MCS_PORT02_AADR }, - {"MCS_PORT02_AAER", MCS_PORT02_AAER }, - {"MCS_PORT02_MCAMOC", MCS_PORT02_MCAMOC }, - {"MCS_PORT02_MCBUSYQ", MCS_PORT02_MCBUSYQ }, - {"MCS_PORT02_MCEBUSCL", MCS_PORT02_MCEBUSCL }, - {"MCS_PORT02_MCEPSQ", MCS_PORT02_MCEPSQ }, - {"MCS_PORT02_MCERRINJ", MCS_PORT02_MCERRINJ }, - {"MCS_PORT02_MCP0XLT0", MCS_PORT02_MCP0XLT0 }, - {"MCS_PORT02_MCP0XLT1", MCS_PORT02_MCP0XLT1 }, - {"MCS_PORT02_MCP0XLT2", MCS_PORT02_MCP0XLT2 }, - {"MCS_PORT02_MCPERF0", MCS_PORT02_MCPERF0 }, - {"MCS_PORT02_MCPERF2", MCS_PORT02_MCPERF2 }, - {"MCS_PORT02_MCPERF3", MCS_PORT02_MCPERF3 }, - {"MCS_PORT02_MCWAT", MCS_PORT02_MCWAT }, - - {"MCS_PORT13_MCAMOC", MCS_PORT13_MCAMOC }, - {"MCS_PORT13_MCBUSYQ", MCS_PORT13_MCBUSYQ }, - {"MCS_PORT13_MCEBUSCL", MCS_PORT13_MCEBUSCL }, - {"MCS_PORT13_MCEBUSEN0", MCS_PORT13_MCEBUSEN0 }, - {"MCS_PORT13_MCEBUSEN1", MCS_PORT13_MCEBUSEN1 }, - {"MCS_PORT13_MCEBUSEN2", MCS_PORT13_MCEBUSEN2 }, - {"MCS_PORT13_MCEBUSEN3", MCS_PORT13_MCEBUSEN3 }, - {"MCS_PORT13_MCEPSQ", MCS_PORT13_MCEPSQ }, - {"MCS_PORT13_MCERRINJ", MCS_PORT13_MCERRINJ }, - {"MCS_PORT13_MCP0XLT0", MCS_PORT13_MCP0XLT0 }, - {"MCS_PORT13_MCP0XLT1", MCS_PORT13_MCP0XLT1 }, - {"MCS_PORT13_MCP0XLT2", MCS_PORT13_MCP0XLT2 }, - {"MCS_PORT13_MCPERF0", MCS_PORT13_MCPERF0 }, - {"MCS_PORT13_MCPERF2", MCS_PORT13_MCPERF2 }, - {"MCS_PORT13_MCPERF3", MCS_PORT13_MCPERF3 }, - {"MCS_PORT13_MCWAT", MCS_PORT13_MCWAT }, }; for (auto r : l_mcs_registers) -- cgit v1.2.1