From 48f839b9b7e30d1d96807e25cb71a35877eb1184 Mon Sep 17 00:00:00 2001 From: Jacob Harvey Date: Thu, 18 Aug 2016 14:12:24 -0500 Subject: Fix DRAM_RTT_WR Change-Id: Ic6c571fff22f8ae9593801265d9465ba8fdd22eb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28476 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Brian R. Silver Reviewed-by: Louis Stermole Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28479 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Stephen M. Cprek --- src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/import/chips/p9/procedures/hwp/memory') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C index ff88068ca..4927bbe3b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C @@ -140,6 +140,10 @@ fapi2::ReturnCode mrs02(const fapi2::Target& i_target, l_rtt_wr_buffer = 0b010; break; + case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM80: + l_rtt_wr_buffer = 0b100; + break; + case fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_RTT_WR_OHM120: l_rtt_wr_buffer = 0b001; break; -- cgit v1.2.1