From 19eb5718ee472094163e55b4f02cc3d019ae2215 Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Wed, 17 Aug 2016 11:19:10 -0500 Subject: Fixed eff_config attr generation Attributes generation fixed: read_preamble_train odt_input_buffer Change-Id: Ib23f2164dfee9386fa521e541b9baeb6cf5d39e1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28405 Tested-by: Jenkins Server Reviewed-by: ANDRE A. MARIN Tested-by: Hostboot CI Reviewed-by: Brian R. Silver Reviewed-by: Matt K. Light Reviewed-by: William G. Hoffa Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28409 Tested-by: FSP CI Jenkins --- .../chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C | 2 +- .../chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C | 2 +- .../p9/procedures/hwp/memory/lib/eff_config/eff_config.C | 14 ++++++++++---- 3 files changed, 12 insertions(+), 6 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/memory') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C index dec791a4e..01f6cf413 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C @@ -61,7 +61,7 @@ mrs04_data::mrs04_data( const fapi2::Target& i_target, iv_vref_mon(0), iv_cs_cmd_latency(0), iv_ref_abort(0), - iv_rd_pre_train_mode(0), + iv_rd_pre_train_mode(fapi2::ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE), iv_rd_preamble(0), iv_wr_preamble(0), iv_ppr(0) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index 5a6f963d6..74acd2116 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -58,7 +58,7 @@ mrs05_data::mrs05_data( const fapi2::Target& i_target, iv_ca_parity_latency(0), iv_crc_error_clear(0), iv_ca_parity_error_status(0), - iv_odt_input_buffer(0), + iv_odt_input_buffer(fapi2::ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED), iv_ca_parity(0), iv_data_mask(0), iv_write_dbi(0), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C index f3bbdaf84..f5c078782 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C @@ -2037,7 +2037,8 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::odt_input_buffer(const fapi2::Target& i_target) { - // TK - RIT skeleton. Need to finish - AAM + // keeping this value as 0x01, given that we know that that works in sim + constexpr uint8_t SIM_VALUE = 0x01; std::vector l_attrs_odt_input_buffer(PORTS_PER_MCS, 0); // Targets @@ -2047,9 +2048,15 @@ fapi2::ReturnCode eff_config::odt_input_buffer(const fapi2::Target(), is_sim) ); + + FAPI_TRY( eff_odt_input_buff(l_mcs, l_attrs_odt_input_buffer.data()) ); - l_attrs_odt_input_buffer[l_port_num] = 0x01; + //sim vs actual hardware value + l_attrs_odt_input_buffer[l_port_num] = is_sim ? SIM_VALUE : fapi2::ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_ODT_INPUT_BUFF, l_mcs, @@ -2176,14 +2183,13 @@ fapi_try_exit: /// fapi2::ReturnCode eff_config::read_preamble_train(const fapi2::Target& i_target) { - // TK - RIT skeleton. Need to finish - AAM const auto l_mcs = find_target(i_target); const auto l_port_num = index( find_target(i_target) ); std::vector l_attrs_rd_preamble_train(PORTS_PER_MCS, 0); FAPI_TRY( eff_rd_preamble_train(l_mcs, l_attrs_rd_preamble_train.data()) ); - l_attrs_rd_preamble_train[l_port_num] = 0x00; + l_attrs_rd_preamble_train[l_port_num] = fapi2::ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_RD_PREAMBLE_TRAIN, l_mcs, -- cgit v1.2.1