From afeaf784ddb685f76b311bb17425f1c1b68c0b5f Mon Sep 17 00:00:00 2001 From: Matthew Hickman Date: Mon, 15 Apr 2019 16:32:46 -0500 Subject: Fixed the ccs port merge conflicts and added lab code Change-Id: Ic4f40a145452f8e95d99e18f040517499a5597ed Original-Change-Id: I665ea2460a5ace289b17ae868b07a8876b65a0c8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75236 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Dev-Ready: STEPHEN GLANCY Tested-by: PPE CI Reviewed-by: Louis Stermole Tested-by: HWSV CI Reviewed-by: Mark Pizzutillo Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81323 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R Geddes --- .../lib/workarounds/quad_encode_workarounds.C | 7 ++++--- .../lib/workarounds/quad_encode_workarounds.H | 24 +++++++++++----------- 2 files changed, 16 insertions(+), 15 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/memory/lib') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C index b09ab6f70..9d68afdc0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C @@ -39,7 +39,8 @@ #include #include -#include +#include +#include #include #include #include @@ -105,7 +106,7 @@ const std::vector< uint64_t> shadow_regs_traits<6>::REGS = /// @param[in] i_inst instruction to check for an MRS command /// @return true iff the command contains an MRS command /// -bool is_command_mrs(const ccs::instruction_t& i_inst) +bool is_command_mrs(const ccs::instruction_t& i_inst) { // An MRS command is // 1) at least one chip select active @@ -132,7 +133,7 @@ bool is_command_mrs(const ccs::instruction_t& i_inst) /// @param[in] i_inst instruction to check for an MRS command /// @return true iff the command contains an MRS command /// -bool contains_command_mrs(const std::vector>& i_inst) +bool contains_command_mrs(const std::vector& i_inst) { bool l_contains_mrs = false; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H index cb062e9ac..6ed2316c5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H @@ -42,7 +42,7 @@ #include #include #include -#include +#include #include #include #include @@ -87,21 +87,21 @@ fapi2::ReturnCode check_shadow_register_corruption( const fapi2::Target& i_inst); +bool is_command_mrs(const ccs::instruction_t& i_inst); /// /// @brief Returns true if a vector of commands contains an MRS command /// @param[in] i_inst instruction to check for an MRS command /// @return true iff the command contains an MRS command /// -bool contains_command_mrs(const std::vector>& i_inst); +bool contains_command_mrs(const std::vector& i_inst); /// /// @brief Converts the CCS instructions to the shadow register configuration /// @param[in] i_inst CCS instruction to convert /// @return the register value for the shadow register /// -inline fapi2::buffer convert_to_shadow_reg(const ccs::instruction_t& i_inst) +inline fapi2::buffer convert_to_shadow_reg(const ccs::instruction_t& i_inst) { fapi2::buffer l_arr0(i_inst.arr0); mss::reverse(l_arr0); @@ -137,7 +137,7 @@ class shadow_regs_traits<0> /// @return FAPI2_RC_SUCCESS iff OK /// static inline fapi2::ReturnCode mrs_gen(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint8_t LR_2666_MARGIN_ADJUST = 2; @@ -188,7 +188,7 @@ class shadow_regs_traits<1> /// @return FAPI2_RC_SUCCESS iff OK /// static inline fapi2::ReturnCode mrs_gen(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { return mss::ddr4::mrs01(i_target, io_inst, i_rank); @@ -214,7 +214,7 @@ class shadow_regs_traits<2> /// @return FAPI2_RC_SUCCESS iff OK /// static inline fapi2::ReturnCode mrs_gen(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { return mss::ddr4::mrs02(i_target, io_inst, i_rank); @@ -240,7 +240,7 @@ class shadow_regs_traits<3> /// @return FAPI2_RC_SUCCESS iff OK /// static inline fapi2::ReturnCode mrs_gen(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { return mss::ddr4::mrs03(i_target, io_inst, i_rank); @@ -266,7 +266,7 @@ class shadow_regs_traits<4> /// @return FAPI2_RC_SUCCESS iff OK /// static inline fapi2::ReturnCode mrs_gen(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { return mss::ddr4::mrs04(i_target, io_inst, i_rank); @@ -292,7 +292,7 @@ class shadow_regs_traits<5> /// @return FAPI2_RC_SUCCESS iff OK /// static inline fapi2::ReturnCode mrs_gen(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { return mss::ddr4::mrs05(i_target, io_inst, i_rank); @@ -318,7 +318,7 @@ class shadow_regs_traits<6> /// @return FAPI2_RC_SUCCESS iff OK /// static inline fapi2::ReturnCode mrs_gen(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { return mss::ddr4::mrs06(i_target, io_inst, i_rank); @@ -342,7 +342,7 @@ fapi2::ReturnCode fix_shadow_register_corruption_mr( const fapi2::Target l_inst; + ccs::instruction_t l_inst; const auto& l_mca = mss::find_target(i_target); // Converts this to DIMM rank. just. in. case. -- cgit v1.2.1