From 546c014e9b53011575917fcb66238ba28fcf5fe5 Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Fri, 12 Oct 2018 14:09:27 -0500 Subject: Adds LRDIMM DWL training step Change-Id: I0fe9a777722cec85249a558a37a90b1eaaf7cd0a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67525 Tested-by: Jenkins Server Reviewed-by: Louis Stermole Tested-by: HWSV CI Reviewed-by: ANDRE A. MARIN Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68560 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- .../hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H | 68 ++++++++++++++++++++++ .../p9/procedures/hwp/memory/lib/dimm/mrs_load.H | 3 +- .../hwp/memory/lib/phy/mss_lrdimm_training.C | 43 +------------- .../hwp/memory/lib/phy/mss_lrdimm_training.H | 64 ++++---------------- .../procedures/hwp/memory/lib/phy/mss_training.C | 15 +++++ 5 files changed, 100 insertions(+), 93 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/memory/lib') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H index 3c5671bf4..49d0b68e7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H @@ -1517,6 +1517,40 @@ struct mrs06_data fapi2::ReturnCode mrs_load( const fapi2::Target& i_target, std::vector< ccs::instruction_t >& io_inst); +/// +/// @brief Sets WR LVL mode +/// @param[in] i_target a DIMM target +/// @param[in] i_mode setting for WR LVL mode +/// @param[in,out] io_data data we are modifying MPR mode to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +inline fapi2::ReturnCode set_wr_lvl_mode(const fapi2::Target& i_target, + const mss::states i_mode, + mrs01_data& io_data) +{ + constexpr uint64_t MAX_WR_LVL_MODE = 0b1; + + FAPI_ASSERT( i_mode <= MAX_WR_LVL_MODE, + fapi2::MSS_BAD_MR_PARAMETER() + .set_MR_NUMBER(MRS_LOAD) + .set_PARAMETER(WR_LVL) + .set_PARAMETER_VALUE(i_mode) + .set_DIMM_IN_ERROR(i_target), + "%s Invalid WR LVL Mode recieved: %d. Max encoding allowed: %d.", + mss::c_str(i_target), + i_mode, + MAX_WR_LVL_MODE); + + // Update field if input check passes + io_data.iv_wl_enable = i_mode == mss::states::ON ? + fapi2::ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE : + fapi2::ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE; + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + /// /// @brief Set MPR Mode /// @param[in] i_target a DIMM target @@ -1683,6 +1717,40 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Makes CCS instruction to set WR LVL Mode +/// @tparam T TargetType of the CCS instruction +/// @param[in] i_target a DIMM target +/// @param[in] i_mode setting for WR LVL mode +/// @param[in] i_rank DIMM rank +/// @param[in,out] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< fapi2::TargetType T > +fapi2::ReturnCode wr_lvl(const fapi2::Target& i_target, + const mss::states i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) +{ + // Spec states we need to use tmod for our delay, so we do + const uint64_t l_delay = mss::tmod(i_target); + + mrs01_data l_data(i_target, fapi2::current_err); + FAPI_TRY(fapi2::current_err, "%s. Failed to initialize mrs01_data for set_wr_lvl_mode", mss::c_str(i_target) ); + + FAPI_TRY( set_wr_lvl_mode(i_target, i_mode, l_data), + "%s. Failed set_wr_lvl_mode() with a setting of %d", + mss::c_str(i_target), i_mode); + + // Make MRS CCS inst + FAPI_TRY( mrs_engine(i_target, l_data, i_rank, l_delay, io_inst), + "Failed to send MRS01 on %s, rank: %d, delay (in cycles): %d", + mss::c_str(i_target), i_rank, l_delay); + +fapi_try_exit: + return fapi2::current_err; +} + /// /// @brief Makes CCS instruction to set MPR Mode /// @tparam T TargetType of the CCS instruction diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H index bcfdb2803..2b0418cfb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -69,6 +69,7 @@ enum mrs_bad_field RTT_WR = 12, MPR_PAGE = 13, MPR_MODE = 14, + WR_LVL = 15, // Following is for MR_NUMBER entry into the BAD_MR_PARAM ffdc // Set to random value so it won't be confused with an actual MR number diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C index 5e127efcb..a9fed2834 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C @@ -48,6 +48,8 @@ #include #include #include +#include +#include namespace mss { @@ -57,7 +59,6 @@ namespace training namespace lrdimm { - /// /// @brief Swizzles a DQ from the MC perspective to the DIMM perspective /// @param[in] i_target the MCA target on which to operate @@ -244,7 +245,7 @@ fapi_try_exit: /// @param[in] i_target - the MCA target on which to operate /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok /// -fapi2::ReturnCode mrep::execute_nttm_mode_read(const fapi2::Target& i_target) const +fapi2::ReturnCode execute_nttm_mode_read(const fapi2::Target& i_target) { mss::ccs::program l_program; const auto& l_mcbist = mss::find_target(i_target); @@ -687,44 +688,6 @@ uint64_t mrep::calculate_cycles( const fapi2::Target& i_ return 0; } -/// -/// @brief Sets up and runs the calibration step -/// @param[in] i_target - the MCA target on which to operate -/// @param[in] i_rp - the rank pair -/// @param[in] i_abort_on_error - whether or not we are aborting on cal error -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode dwl::run( const fapi2::Target& i_target, - const uint64_t i_rp, - const uint8_t i_abort_on_error ) const -{ - return fapi2::FAPI2_RC_SUCCESS; -} - -/// -/// @brief Executes a cal step with workarounds -/// @param[in] i_target - the MCA target on which to operate -/// @param[in] i_rp - the rank pair -/// @param[in] i_abort_on_error - whether or not we are aborting on cal error -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode dwl::execute( const fapi2::Target& i_target, - const uint64_t i_rp, - const uint8_t i_abort_on_error ) const -{ - return fapi2::FAPI2_RC_SUCCESS; -} - -/// -/// @brief Calculates the number of cycles a given calibration step will take -/// @param[in] i_target - the MCA target on which to operate -/// @return l_cycles - the number of cycles a given calibration step wil take -/// -uint64_t dwl::calculate_cycles( const fapi2::Target& i_target ) const -{ - return 0; -} - /// /// @brief Sets up and runs the calibration step /// @param[in] i_target - the MCA target on which to operate diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H index 7805a95d5..fafb498ae 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H @@ -51,6 +51,11 @@ #include #include +// Disables LRDIMM support for HB +#ifndef __HOSTBOOT_MODULE + #define LRDIMM_CAPABLE 1 +#endif + namespace mss { @@ -463,13 +468,6 @@ class mrep : public step i_mrep_result, mss::ddr4::pba::commands& o_container) const; - /// - ///// @brief Does a CCS NTTM mode read - ///// @param[in] i_target - the MCA target on which to operate - ///// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok - ///// - fapi2::ReturnCode execute_nttm_mode_read(const fapi2::Target& i_target) const; - /// /// @brief analyze with each nibble /// @param[in] i_target the MCA target @@ -609,51 +607,6 @@ class mrep : public step }; -/// -/// @brief DWL training step -/// -class dwl : public step -{ - public: - dwl() : - step("DWL") - {} - - /// - /// @brief Default virtual destructor - /// - ~dwl() = default; - - /// - /// @brief Sets up and runs the calibration step - /// @param[in] i_target - the MCA target on which to operate - /// @param[in] i_rp - the rank pair - /// @param[in] i_abort_on_error - whether or not we are aborting on cal error - /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok - /// - fapi2::ReturnCode run( const fapi2::Target& i_target, - const uint64_t i_rp, - const uint8_t i_abort_on_error ) const; - - /// - /// @brief Executes a cal step with workarounds - /// @param[in] i_target - the MCA target on which to operate - /// @param[in] i_rp - the rank pair - /// @param[in] i_abort_on_error - whether or not we are aborting on cal error - /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok - /// - fapi2::ReturnCode execute( const fapi2::Target& i_target, - const uint64_t i_rp, - const uint8_t i_abort_on_error ) const; - - /// - /// @brief Calculates the number of cycles a given calibration step will take - /// @param[in] i_target - the MCA target on which to operate - /// @return l_cycles - the number of cycles a given calibration step wil take - /// - uint64_t calculate_cycles( const fapi2::Target& i_target ) const; -}; - /// /// @brief MPR training step /// @@ -833,6 +786,13 @@ void deconfigure_steps(const uint8_t i_dimm_type, const bool i_sim, fapi2::buffer& io_cal_steps); +/// +/// @brief Does a CCS NTTM mode read +/// @param[in] i_target - the MCA target on which to operate +/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok +/// +fapi2::ReturnCode execute_nttm_mode_read(const fapi2::Target& i_target); + } // ns training } // ns lrdimm diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index d6e9d06ec..14e3c1780 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -59,6 +59,10 @@ #include #include +#ifdef LRDIMM_CAPABLE + #include +#endif + namespace mss { @@ -1221,6 +1225,17 @@ std::vector> steps_factory(const fapi2::buffer& l_steps.push_back(std::make_shared()); } +#ifdef LRDIMM_CAPABLE + + // DWL + if(i_cal_steps.getBit()) + { + FAPI_INF("LRDIMM: DWL is enabled"); + l_steps.push_back(std::make_shared()); + } + +#endif + // WR LVL if(i_cal_steps.getBit()) { -- cgit v1.2.1