From c00a806435284d3ffd4eb1e6e1142ac8723a8ab2 Mon Sep 17 00:00:00 2001 From: Andre Marin Date: Thu, 11 May 2017 11:28:21 -0500 Subject: Remove ZQCAL redundant CCS inst, move to draminit_training Lab requested to move ZQCL to draminit_training to control (with granularity) all enabled cal steps from an attribute in training. Also removing redundant ZQCAL being sent out for both a-side/b-side and addr_mirroring since this only applies to MRS cmds. Added new attribute proposal for CAL_STEPS_ENABLE to account for LRDIMM training steps and more control bits such as INITIAL_PAT_WR and WR_VRE_LATCH Change-Id: Ibb758af74966a5dd659bf3dda86f283f73956bca Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38648 Reviewed-by: Louis Stermole Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: JACOB L. HARVEY Reviewed-by: Matt K. Light Reviewed-by: Thi N. Tran Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38650 Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins --- .../chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H index aa0aba569..ff41fc8d6 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H @@ -278,7 +278,7 @@ fapi2::ReturnCode rd_vref_vref_sense_setup( const fapi2::Target& i_target, - const fapi2::buffer& i_cal_steps_enabled ); + const fapi2::buffer& i_cal_steps_enabled ); namespace dqs_align { -- cgit v1.2.1