From ba2cdc25cb8894d3899b151b8e2a6c7745ee3e50 Mon Sep 17 00:00:00 2001 From: Andre Marin Date: Thu, 17 Mar 2016 16:52:26 -0500 Subject: Add spd cache, fix unit tests, and eff_config prototype Conflicts: chips/p9/procedures/hwp/memory/lib/eff_config/eff_config.C chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H chips/p9/procedures/hwp/memory/p9_mss_eff_config.C chips/p9/procedures/hwp/memory/tests/mss_eff_config_ut.C chips/p9/procedures/hwp/memory/tests/mss_spd_ut.C Change-Id: I59ec92f29db8f40c73a255030d7cb9e68a200671 Original-Change-Id: Ibe24994444dc32cb852be970eeda18cb6e3c804e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22214 Tested-by: Hostboot CI Tested-by: Jenkins Server Reviewed-by: Louis Stermole Reviewed-by: Brian R. Silver Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22789 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/memory/lib/spd/spd_decoder.C | 218 +++++++++++------- .../p9/procedures/hwp/memory/lib/spd/spd_decoder.H | 248 +++++++++++---------- 2 files changed, 264 insertions(+), 202 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/spd') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C index 00c4c6419..a7eef6466 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C @@ -27,12 +27,15 @@ // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: HB:FSP +#include +#include #include #include -#include "../utils/conversions.H" -#include "../utils/find.H" -#include "spd_decoder.H" +#include +#include +#include +#include using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -45,8 +48,6 @@ namespace mss namespace spd { -// Note: IBM's implementation of std::map is not thread safe - // ========================================================= // Byte 0 maps // Item JC-45-2220.01x @@ -401,12 +402,18 @@ static const std::vector > FINE_TIMEBASE_MAP = ///////////////////////// -// Static member functions implementation +// Non-member function implementations +///////////////////////// +// +// Why not static member functions? Literature states +// that static member functions may reduce class +// encapsulation, hence, non-member functions are preferred. +// But I can be convinced otherwise - AAM ///////////////////////// /// /// @brief Decodes SPD Revision encoding level -/// @param[in] i_target FAPI2 DIMM target +/// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value revision number /// @return fapi2::ReturnCode @@ -415,9 +422,9 @@ static const std::vector > FINE_TIMEBASE_MAP = /// @note Page 14-15 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder::rev_encoding_level(const fapi2::Target& i_target, - const uint8_t* i_spd_data, - uint8_t& o_value) +fapi2::ReturnCode rev_encoding_level(const fapi2::Target& i_target, + const uint8_t* i_spd_data, + uint8_t& o_value) { constexpr size_t BYTE_INDEX = 1; constexpr size_t UNDEFINED = 0xF; // per JEDEC spec this value is undefined @@ -457,7 +464,7 @@ fapi_try_exit: /// /// @brief Decodes SPD Revision additions level -/// @param[in] i_target FAPI2 DIMM target +/// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value revision number /// @return fapi2::ReturnCode @@ -466,9 +473,9 @@ fapi_try_exit: /// @note Page 14-15 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder::rev_additions_level(const fapi2::Target& i_target, - const uint8_t* i_spd_data, - uint8_t& o_value) +fapi2::ReturnCode rev_additions_level(const fapi2::Target& i_target, + const uint8_t* i_spd_data, + uint8_t& o_value) { constexpr size_t BYTE_INDEX = 1; constexpr size_t UNDEFINED = 0xF; // per JEDEC spec this value is undefined @@ -508,8 +515,8 @@ fapi_try_exit: /// /// @brief Decodes base module type (DIMM type) from SPD -/// @param[in] i_target -/// @param[in] i_spd_data PD blob +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD blob /// @param[out] o_value /// @return fapi2::ReturnCode /// @note Decodes SPD Byte 3 (bits 0~3) @@ -517,9 +524,9 @@ fapi_try_exit: /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// -fapi2::ReturnCode decoder::base_module_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, - uint8_t& o_value) +fapi2::ReturnCode base_module_type(const fapi2::Target& i_target, + const uint8_t* i_spd_data, + uint8_t& o_value) { constexpr size_t BYTE_INDEX = 3; uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; @@ -556,14 +563,14 @@ fapi_try_exit: /// /// @brief Object factory to select correct decoder based on SPD revision & dimm type -/// @param[in] i_target FAPI2 DIMM target -/// @param[in] i_spd_data SPD blob -/// @param[out] o_value shared pointer to the factory object +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data +/// @param[out] o_fact_obj shared pointer to the factory object /// @return fapi2::ReturnCode /// -fapi2::ReturnCode decoder::factory(const fapi2::Target& i_target, - const uint8_t* i_spd_data, - std::shared_ptr& o_value) +fapi2::ReturnCode factory(const fapi2::Target& i_target, + const uint8_t* i_spd_data, + std::shared_ptr& o_fact_obj) { uint8_t l_dimm_type = 0; uint8_t l_encoding_rev = 0; @@ -590,7 +597,7 @@ fapi2::ReturnCode decoder::factory(const fapi2::Target& { case 0: case 1: - o_value = std::make_shared(); + o_fact_obj = std::make_shared(); break; default: @@ -634,13 +641,55 @@ fapi_try_exit: } +/// +/// @brief Creates factory object & SPD data caches +/// @param[in] i_target controller target +/// @param[out] o_factory_caches map of factory objects with a dimm pos. key +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode populate_decoder_caches( const fapi2::Target& i_target, + std::map >& o_factory_caches) +{ + size_t l_spd_size = 0; + std::shared_ptr l_pDecoder; + + for( const auto& l_mca : i_target.getChildren() ) + { + for( const auto& l_dimm : l_mca.getChildren() ) + { + // Retrieve SPD size + FAPI_TRY( getSPD(l_dimm, nullptr, l_spd_size) ); + + { + // Retrieve SPD data + uint8_t* l_spd_data = new uint8_t[l_spd_size]; + FAPI_TRY( getSPD(l_dimm, l_spd_data, l_spd_size) ); + + // Retrieve factory object instance & populate spd data for that instance + FAPI_TRY( factory(l_dimm, l_spd_data, l_pDecoder) ); + + // Destructor for shared_ptr calls delete, has undefined behavior + // So we use a default destruction policy for array types that uses delete[] + // If F/W doesn't support this we can include a custom delete in lieu of default_delete + l_pDecoder->iv_spd_data = std::shared_ptr(l_spd_data, std::default_delete()); + + // Populate spd caches maps based on dimm pos + o_factory_caches.emplace(std::make_pair(mss::pos(l_dimm), l_pDecoder)); + } + } + } + +fapi_try_exit: + return fapi2::current_err; +} + ///////////////////////// // Member Method implementation ///////////////////////// /// /// @brief Decodes number of used SPD bytes -/// @param[in] i_target FAPI2 DIMM target +/// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value number of SPD bytes used /// @return fapi2::ReturnCode @@ -692,7 +741,7 @@ fapi_try_exit: /// /// @brief Decodes total number of SPD bytes -/// @param[in] i_target FAPI2 DIMM target +/// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value number of total SPD bytes /// @return fapi2::ReturnCode @@ -740,7 +789,7 @@ fapi_try_exit: /// /// @brief Decodes DRAM Device Type -/// @param[in] i_target FAPI2 DIMM target +/// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value dram device type enumeration /// @return fapi2::ReturnCode @@ -753,7 +802,6 @@ fapi2::ReturnCode decoder::dram_device_type(const fapi2::Target #include +#include +#include namespace mss { @@ -343,79 +345,21 @@ class decoder { public: + std::shared_ptr iv_spd_data; + // Constructor decoder() = default; // Deconstructor virtual ~decoder() = default; - - ///////////////////////// - // Static members functions - ///////////////////////// - - /// - /// @brief Decodes SPD Revision encoding level - /// @param[in] i_target FAPI2 DIMM target - /// @param[in] i_spd_data SPD blob - /// @param[out] o_value revision number - /// @return fapi2::ReturnCode - /// @note Decodes SPD Byte 1 (3~0). - /// @note Item JC-45-2220.01x - /// @note Page 14-15 - /// @note DDR4 SPD Document Release 3 - /// - static fapi2::ReturnCode rev_encoding_level(const fapi2::Target& i_target, - const uint8_t* i_spd_data, - uint8_t& o_value); - /// - /// @brief Decodes SPD Revision additions level - /// @param[in] i_target FAPI2 DIMM target - /// @param[in] i_spd_data SPD blob - /// @param[out] o_value revision number - /// @return fapi2::ReturnCode - /// @note Decodes SPD Byte 1 (bits 7~4). - /// @note Item JC-45-2220.01x - /// @note Page 14-15 - /// @note DDR4 SPD Document Release 3 - /// - static fapi2::ReturnCode rev_additions_level(const fapi2::Target& i_target, - const uint8_t* i_spd_data, - uint8_t& o_value); - - /// - /// @brief Decodes base module type (DIMM type) from SPD - /// @param[in] i_target FAPI2 DIMM target - /// @param[in] i_spd_data SPD blob - /// @param[out] o_value - /// @return fapi2::ReturnCode - /// @note Decodes SPD Byte 3 (bits 3~0) - /// @note Item JC-45-2220.01x - /// @note Page 17 - /// @note DDR4 SPD Document Release 3 - /// - static fapi2::ReturnCode base_module_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, - uint8_t& o_value); - - /// - /// @brief Object factory to select correct decoder based on SPD revision & dimm type - /// @param[in] i_target FAPI2 DIMM target - /// @param[in] i_spd_data SPD blob - /// @param[out] o_value shared pointer to the factory object - /// @return fapi2::ReturnCode - /// - static fapi2::ReturnCode factory(const fapi2::Target& i_target, - const uint8_t* i_spd_data, - std::shared_ptr& o_value); - ///////////////////////// // Member Methods ///////////////////////// /// /// @brief Decodes number of used SPD bytes - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value number of SPD bytes used /// @return fapi2::ReturnCode @@ -430,7 +374,7 @@ class decoder /// /// @brief Decodes total number of SPD bytes - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value number of total SPD bytes /// @return fapi2::ReturnCode @@ -445,7 +389,7 @@ class decoder /// /// @brief Decodes DRAM Device Type - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value dram device type enumeration /// @return fapi2::ReturnCode @@ -488,7 +432,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes SDRAM density from SPD - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value SDRAM density in GBs /// @return fapi2::ReturnCode @@ -502,7 +446,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes number of SDRAM banks from SPD - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value Number of SDRAM banks /// @return fapi2::ReturnCode @@ -517,7 +461,7 @@ class decoder /// /// @brief Decodes number of SDRAM bank groups from SPD - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value Number of SDRAM bank groups /// @return fapi2::ReturnCode @@ -531,7 +475,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes number of SDRAM column address bits - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 5 (bits 2~0) @@ -544,7 +488,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes number of SDRAM row address bits - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 5 (bits 5~3) @@ -557,7 +501,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes Primary SDRAM signal loading - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 6 (bits 1~0) @@ -570,7 +514,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes Primary SDRAM die count - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 6 (bits 6~4) @@ -583,7 +527,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes Primary SDRAM package type - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 6 (bit 7) @@ -596,7 +540,7 @@ class decoder uint8_t& o_value); /// /// @brief Decode SDRAM Maximum activate count - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 7 (bits 3~0) @@ -622,7 +566,7 @@ class decoder uint32_t& o_value); /// /// @brief Decode Soft post package repair (soft PPR) - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 9 (bit 5) @@ -635,7 +579,7 @@ class decoder uint8_t& o_value); /// /// @brief Decode Post package repair (PPR) - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 9 (bits 7~6) @@ -648,7 +592,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes Secondary SDRAM signal loading - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 10 (bits 1~0) @@ -661,7 +605,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes Secondary DRAM Density Ratio - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 10 (bits 3~2) @@ -674,7 +618,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes Secondary SDRAM die count - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 10 (bits 6~4) @@ -687,7 +631,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes Secondary SDRAM package type - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @return fapi2::ReturnCode /// @note SPD Byte 10 (bit 7) @@ -700,7 +644,7 @@ class decoder uint8_t& o_value); /// /// @brief Decode Module Nominal Voltage, VDD - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if 1.2V is operable /// @return fapi2::ReturnCode @@ -714,7 +658,7 @@ class decoder uint8_t& o_value); /// /// @brief Decode Module Nominal Voltage, VDD - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if 1.2V is endurant /// @return fapi2::ReturnCode @@ -728,7 +672,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes SDRAM device width - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value device width in bits /// @return fapi2::ReturnCode @@ -742,7 +686,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes number of package ranks per DIMM - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value number of package ranks per DIMM /// @return fapi2::ReturnCode @@ -756,7 +700,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes Rank Mix - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value rank mix value from SPD /// @return fapi2::ReturnCode @@ -770,7 +714,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes primary bus width - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value primary bus width in bits /// @return fapi2::ReturnCode @@ -784,7 +728,7 @@ class decoder uint8_t& o_value); /// /// @brief Decodes bus width extension - /// @param[in] i_target FAPI2 DIMM targetn + /// @param[in] i_target dimm targetn /// @param[in] i_spd_data SPD blob /// @param[out] o_value bus width extension in bits /// @return fapi2::ReturnCode @@ -798,7 +742,7 @@ class decoder uint8_t& o_value); /// /// @brief Decode Module Thermal Sensor - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value thermal sensor value from SPD /// @return fapi2::ReturnCode @@ -812,7 +756,7 @@ class decoder uint8_t& o_value); /// /// @brief Decode Extended Base Module Type - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value extended base module type value from SPD /// @return fapi2::ReturnCode @@ -826,7 +770,7 @@ class decoder uint8_t& o_value); /// /// @brief Decode Fine Timebase - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value fine_timebase from SPD in picoseconds /// @return fapi2::ReturnCode @@ -840,7 +784,7 @@ class decoder int64_t& o_value); /// /// @brief Decode Medium Timebase - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value fine_timebase from SPD in picoseconds /// @return fapi2::ReturnCode @@ -855,7 +799,7 @@ class decoder /// /// /// @brief Decodes SDRAM Minimum Cycle Time in MTB - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmin in MTB units /// @return fapi2::ReturnCode @@ -874,7 +818,7 @@ class decoder /// /// @brief Decodes SDRAM Maximum Cycle Time in MTB - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmax in MTB units /// @return fapi2::ReturnCode @@ -892,7 +836,7 @@ class decoder int64_t& o_value); /// /// @brief Decode CAS Latencies Supported - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value bitmap of supported CAS latencies /// @return fapi2::ReturnCode @@ -906,7 +850,7 @@ class decoder uint64_t& o_value); /// /// @brief Decodes SDRAM Minimum CAS Latency Time in MTB - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tAAmin in MTB units /// @return fapi2::ReturnCode @@ -924,7 +868,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes SDRAM Minimum RAS to CAS Delay Time in MTB - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCDmin in MTB units /// @return fapi2::ReturnCode @@ -942,7 +886,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Row Precharge Delay Time in MTB - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRPmin in MTB units /// @return fapi2::ReturnCode @@ -960,7 +904,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Active to Precharge Delay Time in MTB - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRASmin in MTB units /// @return fapi2::ReturnCode @@ -974,7 +918,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Active to Active/Refresh Delay Time in MTB - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCmin in MTB units /// @return fapi2::ReturnCode @@ -992,7 +936,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 1 - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC1min in MTB units /// @return fapi2::ReturnCode @@ -1006,7 +950,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 2 - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC2min in MTB units /// @return fapi2::ReturnCode @@ -1020,7 +964,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 4 - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC4min in MTB units /// @return fapi2::ReturnCode @@ -1034,7 +978,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Four Activate Window Delay Time - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tFAWmin in MTB units /// @return fapi2::ReturnCode @@ -1048,7 +992,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Minimum Activate to Activate Delay Time - Different Bank Group - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Smin MTB units /// @return fapi2::ReturnCode @@ -1066,7 +1010,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Minimum Activate to Activate Delay Time - Same Bank Group - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Lmin MTB units /// @return fapi2::ReturnCode @@ -1084,7 +1028,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Minimum CAS to CAS Delay Time - Same Bank Group - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCCD_Lmin MTB units /// @return fapi2::ReturnCode @@ -1102,7 +1046,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Minimum Write Recovery Time - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRmin in MTB units /// @return fapi2::ReturnCode @@ -1116,7 +1060,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Minimum Write to Read Time - Different Bank Group - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRT_Smin in MTB units /// @return fapi2::ReturnCode @@ -1131,7 +1075,7 @@ class decoder /// /// @brief Decodes Minimum Write to Read Time - Same Bank Group - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRT_Lmin in MTB units /// @return fapi2::ReturnCode @@ -1145,7 +1089,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum CAS to CAS Delay Time - Same Bank Group - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCCD_Lmin offset in FTB units /// @return fapi2::ReturnCode @@ -1159,7 +1103,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Same Bank Group - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Lmin offset in FTB units /// @return fapi2::ReturnCode @@ -1173,7 +1117,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Different Bank Group - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Smin offset in FTB units /// @return fapi2::ReturnCode @@ -1187,7 +1131,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum Active to Active/Refresh Delay Time - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCmin offset in FTB units /// @return fapi2::ReturnCode @@ -1201,7 +1145,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum Row Precharge Delay Time - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRPmin offset in FTB units /// @return fapi2::ReturnCode @@ -1215,7 +1159,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for SDRAM Minimum RAS to CAS Delay Time - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCDmin offset in FTB units /// @return fapi2::ReturnCode @@ -1229,7 +1173,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for SDRAM Minimum CAS Latency Time - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tAAmin offset in FTB units /// @return fapi2::ReturnCode @@ -1243,7 +1187,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for SDRAM Maximum Cycle Time - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmax offset in FTB units /// @return fapi2::ReturnCode @@ -1257,7 +1201,7 @@ class decoder int64_t& o_value); /// /// @brief Decodes Fine Offset for SDRAM Minimum Cycle Time - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmin offset in FTB units /// @return fapi2::ReturnCode @@ -1272,7 +1216,7 @@ class decoder /// /// @brief Decodes Cyclical Redundancy Code (CRC) for Base Configuration Section - /// @param[in] i_target FAPI2 DIMM target + /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob /// @param[out] o_value crc value from SPD /// @return fapi2::ReturnCode @@ -1286,6 +1230,76 @@ class decoder uint16_t& o_value); };// decoder + +///////////////////////// +// Non-members functions +///////////////////////// + +/// +/// @brief Decodes SPD Revision encoding level +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD blob +/// @param[out] o_value revision number +/// @return fapi2::ReturnCode +/// @note Decodes SPD Byte 1 (3~0). +/// @note Item JC-45-2220.01x +/// @note Page 14-15 +/// @note DDR4 SPD Document Release 3 +/// +fapi2::ReturnCode rev_encoding_level(const fapi2::Target& i_target, + const uint8_t* i_spd_data, + uint8_t& o_value); +/// +/// @brief Decodes SPD Revision additions level +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD blob +/// @param[out] o_value revision number +/// @return fapi2::ReturnCode +/// @note Decodes SPD Byte 1 (bits 7~4). +/// @note Item JC-45-2220.01x +/// @note Page 14-15 +/// @note DDR4 SPD Document Release 3 +/// +fapi2::ReturnCode rev_additions_level(const fapi2::Target& i_target, + const uint8_t* i_spd_data, + uint8_t& o_value); + +/// +/// @brief Decodes base module type (DIMM type) from SPD +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD blob +/// @param[out] o_value +/// @return fapi2::ReturnCode +/// @note Decodes SPD Byte 3 (bits 3~0) +/// @note Item JC-45-2220.01x +/// @note Page 17 +/// @note DDR4 SPD Document Release 3 +/// +fapi2::ReturnCode base_module_type(const fapi2::Target& i_target, + const uint8_t* i_spd_data, + uint8_t& o_value); + +/// +/// @brief Object factory to select correct decoder based on SPD revision & dimm type +/// @param[in] i_target dimm target +/// @param[in] i_spd_data SPD data +/// @param[out] o_fact_obj shared pointer to the factory object +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode factory(const fapi2::Target& i_target, + const uint8_t* i_spd_data, + std::shared_ptr& o_fact_obj); + +/// +/// @brief Creates factory object & SPD data caches +/// @param[in] i_target controller target +/// @param[out] o_factory_caches map of factory objects with a dimm pos key +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode populate_decoder_caches(const fapi2::Target& i_target, + std::map >& o_factory_caches); + + }// spd }// mss -- cgit v1.2.1