From 33cdcd34e6e767c5c199c83fbbcbe46ddc6fe792 Mon Sep 17 00:00:00 2001 From: Andre Marin Date: Thu, 1 Sep 2016 04:31:13 -0500 Subject: Migrate dimm module decoder from rdimm to common dir LRDIMMs and RDIMMs will share the same base dimm module decoder Change-Id: I09ec2e8060ceaccd327714f54092100af05884f4 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29096 Reviewed-by: Brian R. Silver Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Christian R. Geddes Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29097 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins --- .../memory/lib/spd/common/dimm_module_decoder.H | 292 +++++++++++++ .../hwp/memory/lib/spd/common/spd_decoder.H | 464 ++++++++++----------- .../hwp/memory/lib/spd/rdimm/rdimm_decoder.H | 414 ++++-------------- 3 files changed, 593 insertions(+), 577 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/spd') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/dimm_module_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/dimm_module_decoder.H index f131ee49f..cec0698b9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/dimm_module_decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/dimm_module_decoder.H @@ -32,3 +32,295 @@ // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: HB:FSP + + +#ifndef _MSS_DIMM_MODULE_DECODER_H_ +#define _MSS_DIMM_MODULE_DECODER_H_ + +#include +#include + +namespace mss +{ +namespace spd +{ + +/// +/// @class dimm_module_decoder +/// @brief Abstract class for DIMM module SPD DRAM decoders +/// @note This would include for example, RDIMM and LRDIMM +/// +class dimm_module_decoder +{ + public: + + /// + /// @brief default ctor + /// + dimm_module_decoder() = default; + + /// + /// @brief default dtor + /// + virtual ~dimm_module_decoder() = default; + + /// + /// @brief Decodes module nominal height max, in mm + /// @param[out] o_output height range encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 128 (Bits 4~0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 48 + /// + virtual fapi2::ReturnCode max_module_nominal_height(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes front module maximum thickness max, in mm + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 129 (Bits 3~0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 48 + /// + virtual fapi2::ReturnCode front_module_max_thickness(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes back module maximum thickness max, in mm + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 129 (Bits 7~4) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 48 + /// + virtual fapi2::ReturnCode back_module_max_thickness(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes number of registers used on RDIMM + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 131 (Bits 1~0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 50 + /// + virtual fapi2::ReturnCode num_registers_used(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes number of rows of DRAMs on RDIMM + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 131 (Bits 3~2) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 50 + /// + virtual fapi2::ReturnCode num_rows_of_drams(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes heat spreader thermal characteristics + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCEawSS if okay + /// @note SPD Byte 132 (Bits 6~0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 51 + /// + virtual fapi2::ReturnCode heat_spreader_thermal_char(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes heat spreader solution + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 132 (Bit 7) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 51 + /// + virtual fapi2::ReturnCode heat_spreader_solution(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes number of continuation codes + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 133 (bit 6~0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 51 + /// + virtual fapi2::ReturnCode num_continuation_codes(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes manufacturer ID code + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 133 (bit 6~0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 51 + /// + virtual fapi2::ReturnCode manufacturer_id_code(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes register revision number + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 135 (bit 7~0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 51 + /// + virtual fapi2::ReturnCode register_rev_num(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes address mapping from register to dram + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 136 (bit 0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 52 + /// + virtual fapi2::ReturnCode register_to_dram_addr_mapping(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes register output drive strength for CKE signal + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 137 (bit 1~0) + /// @note Item JC-45-2220.01x + /// @note Page 76 + /// @note DDR4 SPD Document Release 4 + /// + virtual fapi2::ReturnCode cke_signal_output_driver(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes register output drive strength for ODT signal + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 137 (bit 3~2) + /// @note Item JC-45-2220.01x + /// @note Page 76 + /// @note DDR4 SPD Document Release 4 + /// + virtual fapi2::ReturnCode odt_signal_output_driver(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes register output drive strength for command/address (CA) signal + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 137 (bit 5~4) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 53 + /// + virtual fapi2::ReturnCode ca_signal_output_driver(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes register output drive strength for chip select (CS) signal + /// @param[out] o_output encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 137 (bit 6~7) + /// @note Item JC-45-2220.01x + /// @note Page 76 + /// @note DDR4 SPD Document Release 4 + /// + virtual fapi2::ReturnCode cs_signal_output_driver(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes register output drive strength for clock (B side) + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 138 (bit 1~0) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 53 + /// + virtual fapi2::ReturnCode b_side_clk_output_driver(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Decodes register output drive strength for clock (A side) + /// @param[out] o_output drive strength encoding from SPD + /// @return FAPI2_RC_SUCCESS if okay + /// @note SPD Byte 138 (bit 3~2) + /// @note Item JEDEC Standard No. 21-C + /// @note DDR4 SPD Document Release 2 + /// @note Page 4.1.2.12 - 53 + /// + virtual fapi2::ReturnCode a_side_clk_output_driver(uint8_t& o_output) + { + o_output = 0; + return fapi2::FAPI2_RC_SUCCESS; + } +}; + +}// spd +}// mss + +#endif //_MSS_DIMM_MODULE_DECODER_H_ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H index 093e1e906..439821411 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/common/spd_decoder.H @@ -54,15 +54,29 @@ namespace mss namespace spd { -enum byte_extract : uint8_t +enum sdram_package_type : uint8_t { - // Byte 0 - BYTES_USED_START = 4, - BYTES_USED_LEN = 4, + // Signal loading + MONOLITHIC = 0, + NON_MONOLITHIC = 1, - BYTES_TOTAL_START = 1, - BYTES_TOTAL_LEN = 3, + // Package Type + UNSPECIFIED = MONOLITHIC, + MULTI_LOAD_STACK = 1, + SINGLE_LOAD_STACK = 2, +}; + +enum nominal_voltage : uint8_t +{ + NOT_OPERABLE = 0, + OPERABLE = 1, + NOT_ENDURANT = 0, + ENDURANT = 1 +}; + +enum factory_byte_extract +{ // Byte 1 ENCODING_LEVEL_START = 0, ENCODING_LEVEL_LEN = 4, @@ -70,313 +84,297 @@ enum byte_extract : uint8_t ADDITIONS_LEVEL_START = 4, ADDITIONS_LEVEL_LEN = 4, - // Byte 2 - Entire byte used - // Byte 3 BASE_MODULE_START = 4, BASE_MODULE_LEN = 4, +}; - HYBRID_MEDIA_START = 1, - HYBRID_MEDIA_LEN = 3, - - HYBRID_START = 0, - HYBRID_LEN = 1, - - // Byte 4 - SDRAM_CAPACITY_START = 4, - SDRAM_CAPACITY_LEN = 4, - - SDRAM_BANKS_START = 2, - SDRAM_BANKS_LEN = 2, - - BANK_GROUP_START = 0, - BANK_GROUP_LEN = 2, - - // Byte 5 - COL_ADDRESS_START = 5, - COL_ADDRESS_LEN = 3, +/// +/// @brief Helper function to extract byte information +/// @tparam I Byte index +/// @tparam S Start bit +/// @tparam L Bit length +/// @return extracted byte (right aligned) +/// +template +inline uint8_t extract_spd_field(const fapi2::Target& i_target, + const std::vector& i_spd_data) +{ + //TODO - RTC:159477 + FAPI_INF("%s SPD data at Byte %d: 0x%llX.", + mss::c_str(i_target), + I, + i_spd_data[I]); - ROW_ADDRESS_START = 2, - ROW_ADDRESS_LEN = 3, + fapi2::buffer l_buffer(i_spd_data[I]); - ADDRESS_RESERVED_START = 0, - ADDRESS_RESERVED_LEN = 2, + // Extracting desired bits + uint8_t l_field_bits = 0; + l_buffer.extractToRight(l_field_bits); - // Byte 6 - PRIM_SIGNAL_LOAD_START = 6, - PRIM_SIGNAL_LOAD_LEN = 2, + return l_field_bits; +} - PACKAGE_RESERVE_START = 4, - PACKAGE_RESERVE_LEN = 2, +/// +/// @class decoder +/// @brief Base SPD DRAM decoder +/// +class decoder +{ + protected: + enum + { + // Byte 0 + BYTES_USED_START = 4, + BYTES_USED_LEN = 4, - PRIM_DIE_COUNT_START = 1, - PRIM_DIE_COUNT_LEN = 3, + BYTES_TOTAL_START = 1, + BYTES_TOTAL_LEN = 3, - PRIM_PACKAGE_TYPE_START = 0, - PRIM_PACKAGE_TYPE_LEN = 1, + // Byte 1 - see factory byte enum + // Byte 2 - Entire byte used - // Byte 7 - MAC_START = 4, - MAC_LEN = 4, + // Byte 3 + HYBRID_MEDIA_START = 1, + HYBRID_MEDIA_LEN = 3, - TMAW_START = 2, - TMAW_LEN = 2, + HYBRID_START = 0, + HYBRID_LEN = 1, - OPT_FEAT_RESERVED_START = 0, - OPT_FEAT_RESERVED_LEN = 2, + // Byte 4 + SDRAM_CAPACITY_START = 4, + SDRAM_CAPACITY_LEN = 4, - // Byte 8 reserved + SDRAM_BANKS_START = 2, + SDRAM_BANKS_LEN = 2, - // Byte 9 - PPR_RESERVED_START = 3, - PPR_RESERVED_LEN = 5, + BANK_GROUP_START = 0, + BANK_GROUP_LEN = 2, - SOFT_PPR_START = 2, - SOFT_PPR_LEN = 1, + // Byte 5 + COL_ADDRESS_START = 5, + COL_ADDRESS_LEN = 3, - PPR_START = 0, - PPR_LEN = 2, + ROW_ADDRESS_START = 2, + ROW_ADDRESS_LEN = 3, - // Byte 10 - SEC_SIGNAL_LOAD_START = 5, - SEC_SIGNAL_LOAD_LEN = 2, + ADDRESS_RESERVED_START = 0, + ADDRESS_RESERVED_LEN = 2, - DENSITY_RATIO_START = 4, - DENSITY_RATIO_LEN = 2, + // Byte 6 + PRIM_SIGNAL_LOAD_START = 6, + PRIM_SIGNAL_LOAD_LEN = 2, - SEC_DIE_COUNT_START = 1, - SEC_DIE_COUNT_LEN = 3, + PACKAGE_RESERVE_START = 4, + PACKAGE_RESERVE_LEN = 2, - SEC_PACKAGE_TYPE_START = 0, - SEC_PACKAGE_TYPE_LEN = 1, + PRIM_DIE_COUNT_START = 1, + PRIM_DIE_COUNT_LEN = 3, - // Byte 11 - OPERABLE_START = 7, - OPERABLE_LEN = 1, + PRIM_PACKAGE_TYPE_START = 0, + PRIM_PACKAGE_TYPE_LEN = 1, - ENDURANT_START = 6, - ENDURANT_LEN = 1, + // Byte 7 + MAC_START = 4, + MAC_LEN = 4, - NOM_VOLT_START = 0, - NOM_VOLT_LEN = 6, + TMAW_START = 2, + TMAW_LEN = 2, - // Byte 12 - SDRAM_WIDTH_START = 5, - SDRAM_WIDTH_LEN = 3, + OPT_FEAT_RESERVED_START = 0, + OPT_FEAT_RESERVED_LEN = 2, - PACKAGE_RANKS_START = 2, - PACKAGE_RANKS_LEN = 3, + // Byte 8 reserved - RANK_MIX_START = 1, - RANK_MIX_LEN = 1, + // Byte 9 + PPR_RESERVED_START = 3, + PPR_RESERVED_LEN = 5, - MODULE_ORG_RESERVED_START = 0, - MODULE_ORG_RESERVED_LEN = 1, + SOFT_PPR_START = 2, + SOFT_PPR_LEN = 1, - // Byte 13 - BUS_WIDTH_START = 5, - BUS_WIDTH_LEN = 3, + PPR_START = 0, + PPR_LEN = 2, - BUS_EXT_WIDTH_START = 3, - BUS_EXT_WIDTH_LEN = 2, + // Byte 10 + SEC_SIGNAL_LOAD_START = 5, + SEC_SIGNAL_LOAD_LEN = 2, - BUS_WIDTH_RESERVED_START = 0, - BUS_WIDTH_RESERVED_LEN = 3, + DENSITY_RATIO_START = 4, + DENSITY_RATIO_LEN = 2, - // Byte 14 - THERM_SENSOR_RESERV_START = 1, - THERM_SENSOR_RESERV_LEN = 7, + SEC_DIE_COUNT_START = 1, + SEC_DIE_COUNT_LEN = 3, - THERM_SENSOR_START = 0, - THERM_SENSOR_LEN = 1, + SEC_PACKAGE_TYPE_START = 0, + SEC_PACKAGE_TYPE_LEN = 1, - // Byte 15 - EXT_MOD_TYPE_START = 5, - EXT_MOD_TYPE_LEN = 3, + // Byte 11 + OPERABLE_START = 7, + OPERABLE_LEN = 1, - EXT_MOD_TYPE_RESERV_START = 0, - EXT_MOD_TYPE_RESERV_LEN = 4, + ENDURANT_START = 6, + ENDURANT_LEN = 1, - // Byte 16 - reserved + NOM_VOLT_START = 0, + NOM_VOLT_LEN = 6, - // Byte 17 - FINE_TIMEBASE_START = 6, - FINE_TIMEBASE_LEN = 2, + // Byte 12 + SDRAM_WIDTH_START = 5, + SDRAM_WIDTH_LEN = 3, - MED_TIMEBASE_START = 4, - MED_TIMEBASE_LEN = 2, + PACKAGE_RANKS_START = 2, + PACKAGE_RANKS_LEN = 3, - TIMEBASE_RESERV_START = 0, - TIMEBASE_RESERV_LEN = 4, + RANK_MIX_START = 1, + RANK_MIX_LEN = 1, - // Byte 18 - Entire byte used - // Byte 19 - Entire byte used + MODULE_ORG_RESERVED_START = 0, + MODULE_ORG_RESERVED_LEN = 1, - // Byte 20-23 - CAS_BYTE_1_START = 56, - CAS_BYTE_1_LEN = 8, - CAS_BYTE_2_START = 48, - CAS_BYTE_2_LEN = 8, - CAS_BYTE_3_START = 40, - CAS_BYTE_3_LEN = 8, - CAS_BYTE_4_START = 32, - CAS_BYTE_4_LEN = 8, + // Byte 13 + BUS_WIDTH_START = 5, + BUS_WIDTH_LEN = 3, - // Byte 24 - Entire byte used - // Byte 25 - Entire byte used - // Byte 26 - Entire byte used + BUS_EXT_WIDTH_START = 3, + BUS_EXT_WIDTH_LEN = 2, - // Byte 27 - TRASMIN_MSN_START = 4, // MSN = most significant nibble - TRASMIN_MSN_LEN = 4, + BUS_WIDTH_RESERVED_START = 0, + BUS_WIDTH_RESERVED_LEN = 3, - TRCMIN_MSN_START = 0, // MSN = most significant nibble - TRCMIN_MSN_LEN = 4, + // Byte 14 + THERM_SENSOR_RESERV_START = 1, + THERM_SENSOR_RESERV_LEN = 7, - // Byte 28 - TRASMIN_LSB_START = 0, // LSB = least significant byte - TRASMIN_LSB_LEN = 8, + THERM_SENSOR_START = 0, + THERM_SENSOR_LEN = 1, - // Byte 29 - TRCMIN_LSB_START = 0, // LSB = least significant byte - TRCMIN_LSB_LEN = 8, + // Byte 15 + EXT_MOD_TYPE_START = 5, + EXT_MOD_TYPE_LEN = 3, - // Byte 30 - TRFC1MIN_LSB_START = 0, - TRFC1MIN_LSB_LEN = 8, + EXT_MOD_TYPE_RESERV_START = 0, + EXT_MOD_TYPE_RESERV_LEN = 4, - // Byte 31 - TRFC1MIN_MSB_START = 0, - TRFC1MIN_MSB_LEN = 8, + // Byte 16 - reserved - // Byte 32 - TRFC2MIN_LSB_START = 0, - TRFC2MIN_LSB_LEN = 8, + // Byte 17 + FINE_TIMEBASE_START = 6, + FINE_TIMEBASE_LEN = 2, - // Byte 33 - TRFC2MIN_MSB_START = 0, - TRFC2MIN_MSB_LEN = 8, + MED_TIMEBASE_START = 4, + MED_TIMEBASE_LEN = 2, - // Byte 34 & Byte 35 - TRFC4MIN_LSB_START = 0, - TRFC4MIN_LSB_LEN = 8, + TIMEBASE_RESERV_START = 0, + TIMEBASE_RESERV_LEN = 4, - TRFC4MIN_MSB_START = 0, - TRFC4MIN_MSB_LEN = 8, + // Byte 18 - Entire byte used + // Byte 19 - Entire byte used - // Byte 36 - TFAWMIN_MSN_START = 4, - TFAWMIN_MSN_LEN = 4, + // Byte 20-23 + CAS_BYTE_1_START = 56, + CAS_BYTE_1_LEN = 8, + CAS_BYTE_2_START = 48, + CAS_BYTE_2_LEN = 8, + CAS_BYTE_3_START = 40, + CAS_BYTE_3_LEN = 8, + CAS_BYTE_4_START = 32, + CAS_BYTE_4_LEN = 8, - // Byte 37 - TFAWMIN_LSB_START = 0, - TFAWMIN_LSB_LEN = 8, + // Byte 24 - Entire byte used + // Byte 25 - Entire byte used + // Byte 26 - Entire byte used - // Byte 38 - Entire byte used - // Byte 39 - Entire byte used - // Byte 40 - Entire byte used + // Byte 27 + TRASMIN_MSN_START = 4, // MSN = most significant nibble + TRASMIN_MSN_LEN = 4, - // Byte 41 - TWRMIN_MSN_START = 4, // MSN = most significant nibble - TWRMIN_MSN_LEN = 4, + TRCMIN_MSN_START = 0, // MSN = most significant nibble + TRCMIN_MSN_LEN = 4, - // Byte 42 - TWRMIN_LSB_START = 0, // LSB = least significant nibble - TWRMIN_LSB_LEN = 8, + // Byte 28 + TRASMIN_LSB_START = 0, // LSB = least significant byte + TRASMIN_LSB_LEN = 8, - // Byte 43 - TWTRMIN_L_MSN_START = 0, // MSN = most significant nibble - TWTRMIN_L_MSN_LEN = 4, + // Byte 29 + TRCMIN_LSB_START = 0, // LSB = least significant byte + TRCMIN_LSB_LEN = 8, - TWTRMIN_S_MSN_START = 4, // MSN = most significant nibble - TWTRMIN_S_MSN_LEN = 4, + // Byte 30 + TRFC1MIN_LSB_START = 0, + TRFC1MIN_LSB_LEN = 8, - // Byte 44 - TWTRMIN_S_LSB_START = 0, // LSB = least significant byte - TWTRMIN_S_LSB_LEN = 8, + // Byte 31 + TRFC1MIN_MSB_START = 0, + TRFC1MIN_MSB_LEN = 8, - // Byte 45 - TWTRMIN_L_LSB_START = 0, - TWTRMIN_L_LSB_LEN = 8, + // Byte 32 + TRFC2MIN_LSB_START = 0, + TRFC2MIN_LSB_LEN = 8, - // Bytes 46 - 59 - reserved + // Byte 33 + TRFC2MIN_MSB_START = 0, + TRFC2MIN_MSB_LEN = 8, - // Bytes 60 - 77 - Connector to SDRAM Bit Mapping ?? + // Byte 34 & Byte 35 + TRFC4MIN_LSB_START = 0, + TRFC4MIN_LSB_LEN = 8, - // Bytes 78 - 116 - reserved + TRFC4MIN_MSB_START = 0, + TRFC4MIN_MSB_LEN = 8, - // Bytes 117 - 125 : Entire byte used + // Byte 36 + TFAWMIN_MSN_START = 4, + TFAWMIN_MSN_LEN = 4, - // Byte 126 - CRC_MSB_START = 0, - CRC_MSB_LEN = 8, + // Byte 37 + TFAWMIN_LSB_START = 0, + TFAWMIN_LSB_LEN = 8, - // Byte 127 - CRC_LSB_START = 0, - CRC_LSB_LEN = 8, + // Byte 38 - Entire byte used + // Byte 39 - Entire byte used + // Byte 40 - Entire byte used - // Bytes 128 ~ 191 Module-Specific Section ?? + // Byte 41 + TWRMIN_MSN_START = 4, // MSN = most significant nibble + TWRMIN_MSN_LEN = 4, - // Bytes 192 ~ 255 Hybrid Memory Architecture Specific Parameters ?? + // Byte 42 + TWRMIN_LSB_START = 0, // LSB = least significant nibble + TWRMIN_LSB_LEN = 8, - // Bytes 256 ~ 319 Extended Function Parameter Block ?? + // Byte 43 + TWTRMIN_L_MSN_START = 0, // MSN = most significant nibble + TWTRMIN_L_MSN_LEN = 4, - // Bytes 320 ~ 383 Module Supplier’s Data ?? -}; + TWTRMIN_S_MSN_START = 4, // MSN = most significant nibble + TWTRMIN_S_MSN_LEN = 4, -enum sdram_package_type : size_t -{ - // Signal loading - MONOLITHIC = 0, - NON_MONOLITHIC = 1, + // Byte 44 + TWTRMIN_S_LSB_START = 0, // LSB = least significant byte + TWTRMIN_S_LSB_LEN = 8, - // Package Type - UNSPECIFIED = MONOLITHIC, - MULTI_LOAD_STACK = 1, - SINGLE_LOAD_STACK = 2, -}; + // Byte 45 + TWTRMIN_L_LSB_START = 0, + TWTRMIN_L_LSB_LEN = 8, -enum nominal_voltage : uint8_t -{ - NOT_OPERABLE = 0, - OPERABLE = 1, + // Bytes 46 - 59 - reserved - NOT_ENDURANT = 0, - ENDURANT = 1 -}; + // Bytes 60 - 77 - Connector to SDRAM Bit Mapping ?? -/// -/// @brief Helper function to extract byte information -/// @tparam I Byte index -/// @tparam S Start bit -/// @tparam L Bit length -/// @return extracted byte (right aligned) -/// -template -inline uint8_t extract_spd_field(const fapi2::Target& i_target, - const std::vector& i_spd_data) -{ - //TODO - RTC:159477 - FAPI_INF("%s SPD data at Byte %d: 0x%llX.", - mss::c_str(i_target), - I, - i_spd_data[I]); + // Bytes 78 - 116 - reserved - fapi2::buffer l_buffer(i_spd_data[I]); + // Bytes 117 - 125 : Entire byte used - // Extracting desired bits - uint8_t l_field_bits = 0; - l_buffer.extractToRight(l_field_bits); + // Byte 126 + CRC_MSB_START = 0, + CRC_MSB_LEN = 8, - return l_field_bits; -} + // Byte 127 + CRC_LSB_START = 0, + CRC_LSB_LEN = 8, + }; -/// -/// @class decoder -/// @brief Base SPD DRAM decoder -/// -class decoder -{ public: std::shared_ptr iv_module_decoder; std::vector iv_spd_data; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder.H index e562b3936..cd8818d67 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/rdimm/rdimm_decoder.H @@ -37,362 +37,88 @@ #define _MSS_RDIMM_DECODER_H_ #include -#include +#include namespace mss { namespace spd { -enum rdimm_byte_extract -{ - // Byte 128 - MODULE_NOM_HEIGHT_START = 3, - MODULE_NOM_HEIGHT_LEN = 5, - RAW_CARD_EXT_START = 0, - RAW_CARD_EXT_LEN = 3, - - // Byte 129 - FRONT_MODULE_THICKNESS_START = 4, - FRONT_MODULE_THICKNESS_LEN = 4, - BACK_MODULE_THICKNESS_START = 0, - BACK_MODULE_THICKNESS_LEN = 4, - - // Byte 130 - REF_RAW_CARD_START = 3, - REF_RAW_CARD_LEN = 5, - REF_RAW_CARD_REV_START = 1, - REF_RAW_CARD_REV_LEN = 2, - REF_RAW_CARD_EXT_START = 0, - REF_RAW_CARD_EXT_LEN = 1, - - // Byte 131 - REGS_USED_START = 6, - REGS_USED_LEN = 2, - ROWS_OF_DRAMS_START = 4, - ROWS_OF_DRAMS_LEN = 2, - - // Byte 132 - HEAT_SPREADER_CHAR_START = 1, - HEAT_SPREADER_CHAR_LEN = 7, - HEAT_SPREADER_SOL_START = 0, - HEAT_SPREADER_SOL_LEN = 1, - - // Byte 133 - CONTINUATION_CODES_START = 1, - CONTINUATION_CODES_LEN = 7, - - // Byte 134 - whole byte taken - // Byte 135 - whole byte taken - - // Byte 136 - ADDR_MAPPING_START = 7, - ADDR_MAPPING_LEN = 1, - - // Byte 137 - CKE_DRIVER_START = 6, - CKE_DRIVER_LEN = 2, - ODT_DRIVER_START = 4, - ODT_DRIVER_LEN = 2, - CA_DRIVER_START = 2, - CA_DRIVER_LEN = 2, - CS_DRIVER_START = 0, - CS_DRIVER_LEN = 2, - - // Byte 138 - YO_Y2_DRIVER_START = 6, - YO_Y2_DRIVER_LEN = 2, - Y1_Y3_DRIVER_START = 4, - Y1_Y3_DRIVER_LEN = 2, - -}; - -enum addr_mapping -{ - STANDARD = 0, - MIRRORED = 1, -}; - -/// -/// @class dimm_module_decoder -/// @brief Abstract class for RDIMM module SPD DRAM decoder -/// -class dimm_module_decoder -{ - public: - - /// - /// @brief default ctor - /// - dimm_module_decoder() = default; - - /// - /// @brief default dtor - /// - virtual ~dimm_module_decoder() = default; - - /// - /// @brief Decodes module nominal height max, in mm - /// @param[out] o_output height range encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 128 (Bits 4~0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 48 - /// - virtual fapi2::ReturnCode max_module_nominal_height(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes front module maximum thickness max, in mm - /// @param[out] o_output encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 129 (Bits 3~0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 48 - /// - virtual fapi2::ReturnCode front_module_max_thickness(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes back module maximum thickness max, in mm - /// @param[out] o_output encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 129 (Bits 7~4) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 48 - /// - virtual fapi2::ReturnCode back_module_max_thickness(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes number of registers used on RDIMM - /// @param[out] o_output encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 131 (Bits 1~0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 50 - /// - virtual fapi2::ReturnCode num_registers_used(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes number of rows of DRAMs on RDIMM - /// @param[out] o_output encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 131 (Bits 3~2) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 50 - /// - virtual fapi2::ReturnCode num_rows_of_drams(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes heat spreader thermal characteristics - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCEawSS if okay - /// @note SPD Byte 132 (Bits 6~0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 51 - /// - virtual fapi2::ReturnCode heat_spreader_thermal_char(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes heat spreader solution - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 132 (Bit 7) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 51 - /// - virtual fapi2::ReturnCode heat_spreader_solution(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes number of continuation codes - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 133 (bit 6~0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 51 - /// - virtual fapi2::ReturnCode num_continuation_codes(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes manufacturer ID code - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 133 (bit 6~0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 51 - /// - virtual fapi2::ReturnCode manufacturer_id_code(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes register revision number - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 135 (bit 7~0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 51 - /// - virtual fapi2::ReturnCode register_rev_num(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes address mapping from register to dram - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 136 (bit 0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 52 - /// - virtual fapi2::ReturnCode register_to_dram_addr_mapping(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes register output drive strength for CKE signal - /// @param[out] o_output encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 137 (bit 1~0) - /// @note Item JC-45-2220.01x - /// @note Page 76 - /// @note DDR4 SPD Document Release 4 - /// - virtual fapi2::ReturnCode cke_signal_output_driver(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes register output drive strength for ODT signal - /// @param[out] o_output encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 137 (bit 3~2) - /// @note Item JC-45-2220.01x - /// @note Page 76 - /// @note DDR4 SPD Document Release 4 - /// - virtual fapi2::ReturnCode odt_signal_output_driver(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes register output drive strength for command/address (CA) signal - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 137 (bit 5~4) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 53 - /// - virtual fapi2::ReturnCode ca_signal_output_driver(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes register output drive strength for chip select (CS) signal - /// @param[out] o_output encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 137 (bit 6~7) - /// @note Item JC-45-2220.01x - /// @note Page 76 - /// @note DDR4 SPD Document Release 4 - /// - virtual fapi2::ReturnCode cs_signal_output_driver(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes register output drive strength for clock (B side) - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 138 (bit 1~0) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 53 - /// - virtual fapi2::ReturnCode b_side_clk_output_driver(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } - - /// - /// @brief Decodes register output drive strength for clock (A side) - /// @param[out] o_output drive strength encoding from SPD - /// @return FAPI2_RC_SUCCESS if okay - /// @note SPD Byte 138 (bit 3~2) - /// @note Item JEDEC Standard No. 21-C - /// @note DDR4 SPD Document Release 2 - /// @note Page 4.1.2.12 - 53 - /// - virtual fapi2::ReturnCode a_side_clk_output_driver(uint8_t& o_output) - { - o_output = 0; - return fapi2::FAPI2_RC_SUCCESS; - } -}; - /// /// @class decoder /// @brief RDIMM module SPD DRAM decoder for rev 1.0 /// class rdimm_decoder_v1_0 : public dimm_module_decoder { + protected: + enum + { + // Byte 128 + MODULE_NOM_HEIGHT_START = 3, + MODULE_NOM_HEIGHT_LEN = 5, + RAW_CARD_EXT_START = 0, + RAW_CARD_EXT_LEN = 3, + + // Byte 129 + FRONT_MODULE_THICKNESS_START = 4, + FRONT_MODULE_THICKNESS_LEN = 4, + BACK_MODULE_THICKNESS_START = 0, + BACK_MODULE_THICKNESS_LEN = 4, + + // Byte 130 + REF_RAW_CARD_START = 3, + REF_RAW_CARD_LEN = 5, + REF_RAW_CARD_REV_START = 1, + REF_RAW_CARD_REV_LEN = 2, + REF_RAW_CARD_EXT_START = 0, + REF_RAW_CARD_EXT_LEN = 1, + + // Byte 131 + REGS_USED_START = 6, + REGS_USED_LEN = 2, + ROWS_OF_DRAMS_START = 4, + ROWS_OF_DRAMS_LEN = 2, + + // Byte 132 + HEAT_SPREADER_CHAR_START = 1, + HEAT_SPREADER_CHAR_LEN = 7, + HEAT_SPREADER_SOL_START = 0, + HEAT_SPREADER_SOL_LEN = 1, + + // Byte 133 + CONTINUATION_CODES_START = 1, + CONTINUATION_CODES_LEN = 7, + + // Byte 134 - whole byte taken + // Byte 135 - whole byte taken + + // Byte 136 + ADDR_MAPPING_START = 7, + ADDR_MAPPING_LEN = 1, + + // Byte 137 + CKE_DRIVER_START = 6, + CKE_DRIVER_LEN = 2, + ODT_DRIVER_START = 4, + ODT_DRIVER_LEN = 2, + CA_DRIVER_START = 2, + CA_DRIVER_LEN = 2, + CS_DRIVER_START = 0, + CS_DRIVER_LEN = 2, + + // Byte 138 + YO_Y2_DRIVER_START = 6, + YO_Y2_DRIVER_LEN = 2, + Y1_Y3_DRIVER_START = 4, + Y1_Y3_DRIVER_LEN = 2, + }; + + enum addr_mapping + { + STANDARD = 0, + MIRRORED = 1, + }; + public: // deleted default ctor rdimm_decoder_v1_0() = delete; -- cgit v1.2.1