From 1a57a4045012fde95a70307cbdf9b99b9b62a2d0 Mon Sep 17 00:00:00 2001 From: Andre Marin Date: Mon, 11 Apr 2016 08:40:22 -0500 Subject: Modify spd decoder API to hold its own SPD data, fix dependicies Change-Id: Ida15c44455c0599deea3b455945ea78cf0ba0a5c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23355 Reviewed-by: Brian R. Silver Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: JACOB L. HARVEY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23357 Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../p9/procedures/hwp/memory/lib/spd/spd_decoder.C | 2026 +++++++++----------- .../p9/procedures/hwp/memory/lib/spd/spd_decoder.H | 377 ++-- 2 files changed, 1074 insertions(+), 1329 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/spd') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C index 666b4c84c..0f3e4297d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.C @@ -414,24 +414,21 @@ static const std::vector > FINE_TIMEBASE_MAP = /// /// @brief Decodes SPD Revision encoding level /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob -/// @param[out] o_value revision number -/// @return fapi2::ReturnCode +/// @param[in] i_spd_data SPD data +/// @param[out] o_value encoding revision num +/// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 1 (3~0). /// @note Item JC-45-2220.01x /// @note Page 14-15 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode rev_encoding_level(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + const std::vector& i_spd_data, uint8_t& o_value) { + // Buffer used for bit manipulation constexpr size_t BYTE_INDEX = 1; - constexpr size_t UNDEFINED = 0xF; // per JEDEC spec this value is undefined uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_bit_fields = 0; - - // Buffer used for bit manipulation fapi2::buffer l_buffer(l_raw_byte); // Trace in the front assists w/ debug @@ -441,21 +438,23 @@ fapi2::ReturnCode rev_encoding_level(const fapi2::Target(l_bit_fields); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - (l_bit_fields != UNDEFINED), - BYTE_INDEX, - l_raw_byte, - "Failed check on SPD rev encoding level") ); + // Check that value is valid + constexpr size_t UNDEFINED = 0xF; // per JEDEC spec this value is undefined + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + (l_bit_fields != UNDEFINED), + BYTE_INDEX, + l_raw_byte, + "Failed check on SPD rev encoding level") ); // Update output only after check passes o_value = l_bit_fields; // Print decoded info FAPI_DBG("%s. Rev - Encoding Level : %d", - c_str(i_target), + mss::c_str(i_target), o_value); fapi_try_exit: @@ -465,24 +464,21 @@ fapi_try_exit: /// /// @brief Decodes SPD Revision additions level /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob -/// @param[out] o_value revision number -/// @return fapi2::ReturnCode +/// @param[in] i_spd_data SPD data +/// @param[out] o_value additions revision num +/// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 1 (bits 7~4). /// @note Item JC-45-2220.01x /// @note Page 14-15 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode rev_additions_level(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + const std::vector& i_spd_data, uint8_t& o_value) { + // Buffer used for bit manipulation constexpr size_t BYTE_INDEX = 1; - constexpr size_t UNDEFINED = 0xF; // per JEDEC spec this value is undefined uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_bit_fields = 0; - - // Buffer used for bit manipulation fapi2::buffer l_buffer(l_raw_byte); // Trace in the front assists w/ debug @@ -492,21 +488,23 @@ fapi2::ReturnCode rev_additions_level(const fapi2::Target(l_bit_fields); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - (l_bit_fields != UNDEFINED), - BYTE_INDEX, - l_raw_byte, - "Failed check on SPD rev encoding level") ); + // Check that value is valid + constexpr size_t UNDEFINED = 0xF; // per JEDEC spec this value is undefined + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + (l_bit_fields != UNDEFINED), + BYTE_INDEX, + l_raw_byte, + "Failed check on SPD rev encoding level") ); // Update output only after check passes o_value = l_bit_fields; // Print decoded info FAPI_DBG("%s. Rev - Additions Level : %d", - c_str(i_target), + mss::c_str(i_target), o_value); fapi_try_exit: @@ -516,23 +514,21 @@ fapi_try_exit: /// /// @brief Decodes base module type (DIMM type) from SPD /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob -/// @param[out] o_value -/// @return fapi2::ReturnCode -/// @note Decodes SPD Byte 3 (bits 0~3) +/// @param[in] i_spd_data SPD data +/// @param[out] o_value base module type +/// @return FAPI2_RC_SUCCESS if okay +/// @note Decodes SPD Byte 3 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode base_module_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + const std::vector& i_spd_data, uint8_t& o_value) { + // Buffer used for bit manipulation constexpr size_t BYTE_INDEX = 3; uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation fapi2::buffer l_spd_buffer(l_raw_byte); // Trace in the front assists w/ debug @@ -542,14 +538,16 @@ fapi2::ReturnCode base_module_type(const fapi2::Target& i_targ l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - bool found_key = find_value_from_key(BASE_MODULE_TYPE_MAP, l_field_bits, o_value); + // Check that value is valid + bool l_is_val_found = find_value_from_key(BASE_MODULE_TYPE_MAP, l_field_bits, o_value); - FAPI_TRY( check::spd::fail_for_invalid_value(i_target, - found_key, + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, BYTE_INDEX, l_field_bits, "Failed check on Base Module Type") ); @@ -563,26 +561,33 @@ fapi_try_exit: } /// -/// @brief Object factory to select correct decoder based on SPD revision & dimm type +/// @brief Object factory to select correct decoder /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD data /// @param[out] o_fact_obj shared pointer to the factory object -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay +/// @note Factory dependent on SPD revision & dimm type /// fapi2::ReturnCode factory(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + const std::vector& i_spd_data, std::shared_ptr& o_fact_obj) { uint8_t l_dimm_type = 0; uint8_t l_encoding_rev = 0; uint8_t l_additions_rev = 0; + if( i_spd_data.empty() ) + { + // This won't work with no data + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + // Get dimm type & revision levels FAPI_TRY( base_module_type(i_target, i_spd_data, l_dimm_type), "Failed to find base module type" ); FAPI_TRY( rev_encoding_level(i_target, i_spd_data, l_encoding_rev), "Failed to find encoding level" ); - FAPI_TRY( rev_additions_level(i_target, i_spd_data, l_additions_rev), + FAPI_TRY( rev_additions_level(i_target, i_spd_data, l_additions_rev), "Failed to find additons level" ); // Get decoder object needed for current dimm type and spd rev @@ -606,7 +611,7 @@ fapi2::ReturnCode factory(const fapi2::Target& i_target break; default: - FAPI_TRY( check::spd::invalid_factory_sel(i_target, + FAPI_TRY( mss::check::spd::invalid_factory_sel(i_target, l_dimm_type, l_encoding_rev, l_additions_rev, @@ -617,7 +622,7 @@ fapi2::ReturnCode factory(const fapi2::Target& i_target break; default: - FAPI_TRY( check::spd::invalid_factory_sel(i_target, + FAPI_TRY( mss::check::spd::invalid_factory_sel(i_target, l_dimm_type, l_encoding_rev, l_additions_rev, @@ -628,7 +633,7 @@ fapi2::ReturnCode factory(const fapi2::Target& i_target break; default: - FAPI_TRY( check::spd::invalid_factory_sel(i_target, + FAPI_TRY( mss::check::spd::invalid_factory_sel(i_target, l_dimm_type, l_encoding_rev, l_additions_rev, @@ -637,6 +642,10 @@ fapi2::ReturnCode factory(const fapi2::Target& i_target } // end dimm type + // If we get here than a correct object reference obtained + // Save off SPD data + o_fact_obj->iv_spd_data = i_spd_data; + fapi_try_exit: return fapi2::current_err; @@ -646,7 +655,7 @@ fapi_try_exit: /// /// @brief Creates factory object & SPD data caches /// @param[in] i_target controller target -/// @param[out] o_factory_caches map of factory objects with a dimm pos. key +/// @param[out] o_factory_caches map of factory objects with a dimm position key /// @return FAPI2_RC_SUCCESS if okay /// @note This specialization is suited for creating a cache with platform /// SPD data. @@ -656,32 +665,32 @@ fapi2::ReturnCode populate_decoder_caches( const fapi2::Target& std::map >& o_factory_caches, const std::shared_ptr& i_pDecoder) { - std::shared_ptr l_pDecoder(i_pDecoder); + // Input decoder for this version of populating cache would get overriden + // so I don't bother with it here + std::shared_ptr l_pDecoder; for( const auto& l_mca : i_target.getChildren() ) { for( const auto& l_dimm : l_mca.getChildren() ) { - size_t l_spd_size = 0; + size_t l_size = 0; + FAPI_TRY( getSPD(l_dimm, nullptr, l_size) ); - // Retrieve SPD size - FAPI_TRY( getSPD(l_dimm, nullptr, l_spd_size) ); { - // Retrieve SPD data - uint8_t* l_spd_data = new uint8_t[l_spd_size]; - FAPI_TRY( getSPD(l_dimm, l_spd_data, l_spd_size) ); + // "Container" for SPD data + std::vector l_spd; + l_spd.resize(l_size); + + // Retrive SPD data + FAPI_TRY( getSPD(l_dimm, l_spd.data(), l_size)) ; // Retrieve factory object instance & populate spd data for that instance - FAPI_TRY( factory(l_dimm, l_spd_data, l_pDecoder) ); + FAPI_TRY( factory(l_dimm, l_spd, l_pDecoder) ); - // Destructor for shared_ptr calls delete, has undefined behavior - // So we use a default destruction policy for array types that uses delete[] - // If F/W doesn't support this we can include a custom delete in lieu of default_delete - l_pDecoder->iv_spd_data = std::shared_ptr( l_spd_data, - std::default_delete() ); // Populate spd caches maps based on dimm pos o_factory_caches.emplace(std::make_pair(mss::pos(l_dimm), l_pDecoder)); } + }// end dimm }// end mca @@ -694,20 +703,27 @@ fapi_try_exit: /// /// @brief Creates factory object & SPD data caches /// @param[in] i_target the dimm target -/// @param[out] o_factory_caches map of factory objects with a dimm pos. key +/// @param[out] o_factory_caches map of factory objects with a dimm position key /// @return FAPI2_RC_SUCCESS if okay /// @note This specialization is suited for creating a cache with custom -/// SPD data. +/// SPD data (e.g. testing custom SPD). /// template<> fapi2::ReturnCode populate_decoder_caches( const fapi2::Target& i_target, std::map >& o_factory_caches, const std::shared_ptr& i_pDecoder) { + if(i_pDecoder == nullptr) + { + // This won't work w/a null parameter + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + // This shouldn't be null so there is a specific decoder we are wanting to populate std::shared_ptr l_pDecoder(i_pDecoder); // Custom decoder provided (usually done for testing) - // Populate custom spd caches maps based internal dimm pos + // Populate custom spd caches maps one dimm at a time o_factory_caches.emplace(std::make_pair( mss::pos(i_target), l_pDecoder) ); // TK - else what do we want here @@ -721,46 +737,40 @@ fapi2::ReturnCode populate_decoder_caches( const fapi2::Target /// /// @brief Decodes number of used SPD bytes /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value number of SPD bytes used -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 0 bits(0~3) /// @note Item JC-45-2220.01x /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::number_of_used_bytes(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint16_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 0; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - uint16_t l_map_value = 0; - - // Buffers used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field_Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(BYTES_USED_MAP, l_field_bits, l_map_value), - BYTE_INDEX, - l_map_value, - "Failed check on SPD total bytes") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(BYTES_USED_MAP, l_field_bits, o_value); - // Don't update output with garbage data until until all tests pass - o_value = l_map_value; + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check on SPD used bytes") ); FAPI_DBG("%s. Bytes Used: %d", mss::c_str(i_target), @@ -773,42 +783,40 @@ fapi_try_exit: /// /// @brief Decodes total number of SPD bytes /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value number of total SPD bytes -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 0 (bits 4~6) /// @note Item JC-45-2220.01x /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::number_of_total_bytes(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint16_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 0; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field_Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(BYTES_TOTAL_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check on SPD total bytes") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(BYTES_TOTAL_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check on SPD total bytes") ); FAPI_DBG("%s. Total Bytes: %d", mss::c_str(i_target), @@ -821,20 +829,18 @@ fapi_try_exit: /// /// @brief Decodes DRAM Device Type /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value dram device type enumeration -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 2 /// @note Item JC-45-2220.01x /// @note Page 16 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::dram_device_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { constexpr size_t BYTE_INDEX = 2; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", @@ -842,13 +848,14 @@ fapi2::ReturnCode decoder::dram_device_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 3; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field_Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(HYBRID_MEDIA_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check on Hybrid Media type") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(HYBRID_MEDIA_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check on Hybrid Media type") ); FAPI_DBG("%s. Hybrid Media: %d", mss::c_str(i_target), @@ -910,7 +915,6 @@ fapi_try_exit: /// /// @brief Decodes hybrid field from SPD /// @param[in] i_target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if module is hybrid /// @return fapi2::ReturnCode /// @note Decodes SPD Byte 3 (bit 7) @@ -919,33 +923,29 @@ fapi_try_exit: /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::hybrid(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 3; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field_Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(HYBRID_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check on hybrid field") ); + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + mss::find_value_from_key(HYBRID_MAP, l_field_bits, o_value), + BYTE_INDEX, + l_field_bits, + "Failed check on hybrid field") ); FAPI_DBG("%s. Hybrid: %d", mss::c_str(i_target), @@ -958,46 +958,41 @@ fapi_try_exit: /// /// @brief Decodes SDRAM density from SPD /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value SDRAM density in GBs -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 4 (bits 0~3) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::sdram_density(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 4; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(i_spd_data[BYTE_INDEX]); - - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(iv_spd_data[BYTE_INDEX]); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); // Check to assure SPD DRAM capacity (map) wont be at invalid values - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(SDRAM_DENSITY_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SPD DRAM capacity") ); + bool l_is_val_found = mss::find_value_from_key(SDRAM_DENSITY_MAP, l_field_bits, o_value); + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for SPD DRAM capacity") ); FAPI_DBG("%s. SDRAM density: %d", mss::c_str(i_target), o_value); @@ -1009,45 +1004,39 @@ fapi_try_exit: /// /// @brief Decodes number of SDRAM banks from SPD /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value Number of SDRAM banks -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 4 (bits 4~5) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::banks(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 4; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(i_spd_data[BYTE_INDEX]); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(iv_spd_data[BYTE_INDEX]); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); // Check to assure SPD DRAM capacity (map) wont be at invalid values - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(BANK_ADDR_BITS_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SPD DRAM banks") ); + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + mss::find_value_from_key(BANK_ADDR_BITS_MAP, l_field_bits, o_value), + BYTE_INDEX, + l_field_bits, + "Failed check for SPD DRAM banks") ); FAPI_DBG("%s. Banks: %d", mss::c_str(i_target), @@ -1060,45 +1049,40 @@ fapi_try_exit: /// /// @brief Decodes number of SDRAM bank groups from SPD /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value Number of SDRAM bank groups -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 4 (bits 6~7) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::bank_groups(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 4; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(i_spd_data[BYTE_INDEX]); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(iv_spd_data[BYTE_INDEX]); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); // Check to assure SPD DRAM capacity (map) wont be at invalid values - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(BANK_GROUP_BITS_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SPD DRAM bank groups") ); + bool l_is_val_found = mss::find_value_from_key(BANK_GROUP_BITS_MAP, l_field_bits, o_value); + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for SPD DRAM bank groups") ); FAPI_DBG("%s. Bank Groups: %d", mss::c_str(i_target), o_value); @@ -1110,44 +1094,40 @@ fapi_try_exit: /// /// @brief Decodes number of SDRAM column address bits /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value number of column address bits -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 5 (bits 2~0) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::column_address_bits(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 5; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(i_spd_data[BYTE_INDEX]); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(iv_spd_data[BYTE_INDEX]); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); // Check to assure SPD DRAM capacity (map) wont be at invalid values - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(COLUMN_ADDRESS_BITS_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SDRAM Column Address Bits") ); + bool l_is_val_found = mss::find_value_from_key(COLUMN_ADDRESS_BITS_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for SDRAM Column Address Bits") ); FAPI_DBG("%s. Number of Column Address Bits: %d", mss::c_str(i_target), @@ -1160,44 +1140,40 @@ fapi_try_exit: /// /// @brief Decodes number of SDRAM row address bits /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value number of row address bits -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 5 (bits 5~3) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::row_address_bits(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 5; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(i_spd_data[BYTE_INDEX]); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(iv_spd_data[BYTE_INDEX]); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); // Check to assure SPD DRAM capacity (map) wont be at invalid values - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(ROW_ADDRESS_BITS_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SDRAM Row Address Bits") ); + bool l_is_val_found = mss::find_value_from_key(ROW_ADDRESS_BITS_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd:: fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for SDRAM Row Address Bits") ); FAPI_DBG("%s. Number of Row Address Bits: %d", mss::c_str(i_target), @@ -1211,43 +1187,40 @@ fapi_try_exit: /// /// @brief Decodes Primary SDRAM signal loading /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing signal loading type -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 6 (bits 1~0) /// @note Item JC-45-2220.01x /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::prim_sdram_signal_loading(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 6; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(PRIM_SIGNAL_LOADING_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Primary SDRAM Signal Loading") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(PRIM_SIGNAL_LOADING_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd:: fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Primary SDRAM Signal Loading") ); FAPI_DBG("%s. Primary SDRAM Signal Loading: %d", mss::c_str(i_target), @@ -1260,43 +1233,40 @@ fapi_try_exit: /// /// @brief Decodes Primary SDRAM die count /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value die count -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 6 (bits 6~4) /// @note Item JC-45-2220.01x /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::prim_sdram_die_count(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 6; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(PRIM_DIE_COUNT_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SDRAM Row Address Bits") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(PRIM_DIE_COUNT_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd:: fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for SDRAM Row Address Bits") ); FAPI_DBG("%s. Number of Row Address Bits: %d", mss::c_str(i_target), @@ -1309,43 +1279,40 @@ fapi_try_exit: /// /// @brief Decodes Primary SDRAM package type /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing package type -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 6 (bit 7) /// @note Item JC-45-2220.01x /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::prim_sdram_package_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 6; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(PRIM_PACKAGE_TYPE_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SDRAM Row Address Bits") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(PRIM_PACKAGE_TYPE_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for SDRAM Row Address Bits") ); FAPI_DBG("%s. Number of Row Address Bits: %d", mss::c_str(i_target), @@ -1359,25 +1326,19 @@ fapi_try_exit: /// /// @brief Decode SDRAM Maximum activate count /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing max activate count -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 7 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::maximum_activate_count(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint32_t& o_value) { - - constexpr size_t BYTE_INDEX = 7; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + constexpr size_t BYTE_INDEX = 7; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", @@ -1386,16 +1347,20 @@ fapi2::ReturnCode decoder::maximum_activate_count(const fapi2::Target l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(MAC_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SDRAM Maximum Active Count (MAC)") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(MAC_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for SDRAM Maximum Active Count (MAC)") ); FAPI_DBG("%s. Maximum Active Count (MAC): %d", mss::c_str(i_target), @@ -1408,43 +1373,40 @@ fapi_try_exit: /// /// @brief Decode SDRAM Maximum activate window (multiplier), tREFI uknown at this point /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value max activate window multiplier -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 7 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::maximum_activate_window_multiplier(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint32_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 7; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); - - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(TMAW_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Maximum Active Window (tMAW)") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(TMAW_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Maximum Active Window (tMAW)") ); FAPI_DBG("%s. Maximum Active Window multiplier: %d", mss::c_str(i_target), @@ -1457,43 +1419,40 @@ fapi_try_exit: /// /// @brief Decode Soft post package repair (soft PPR) /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if soft PPR is supported -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 9 (bit 5) /// @note Item JC-45-2220.01x /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::soft_post_package_repair(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 9; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(SOFT_PPR_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Soft PPR") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(SOFT_PPR_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd:: fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Soft PPR") ); FAPI_DBG("%s. Soft Post Package Repair (Soft PPR): %d", mss::c_str(i_target), @@ -1506,7 +1465,6 @@ fapi_try_exit: /// /// @brief Decode Post package repair (PPR) /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if (hard) PPR is supported /// @return fapi2::ReturnCode /// @note SPD Byte 9 (bits 7~6) @@ -1515,15 +1473,11 @@ fapi_try_exit: /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::post_package_repair(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - - constexpr size_t BYTE_INDEX = 9; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - // Buffer used for bit manipulation + constexpr size_t BYTE_INDEX = 9; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; fapi2::buffer l_spd_buffer(l_raw_byte); // Trace in the front assists w/ debug @@ -1533,16 +1487,19 @@ fapi2::ReturnCode decoder::post_package_repair(const fapi2::Target(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(PPR_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for PPR") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(PPR_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for PPR") ); FAPI_DBG("%s. Post Package Repair (PPR): %d", mss::c_str(i_target), @@ -1556,43 +1513,40 @@ fapi_try_exit: /// /// @brief Decodes Secondary SDRAM signal loading /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing signal loading type -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 10 (bits 1~0) /// @note Item JC-45-2220.01x /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::sec_sdram_signal_loading(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 10; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(SEC_SIGNAL_LOADING_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for SDRAM Row Address Bits") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(SEC_SIGNAL_LOADING_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for SDRAM Row Address Bits") ); FAPI_DBG("%s. Number of Row Address Bits: %d", mss::c_str(i_target), @@ -1605,27 +1559,19 @@ fapi_try_exit: /// /// @brief Decodes Secondary DRAM Density Ratio /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value raw bits from SPD -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 10 (bits 3~2) /// @note Item JC-45-2220.01x /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::sec_dram_density_ratio(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - - constexpr size_t BYTE_INDEX = 10; - constexpr size_t UNDEFINED = 3; // JEDEC map doesn't go beyond 3 - - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + constexpr size_t BYTE_INDEX = 10; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", @@ -1634,16 +1580,20 @@ fapi2::ReturnCode decoder::sec_dram_density_ratio(const fapi2::Target l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - l_field_bits != UNDEFINED, - BYTE_INDEX, - l_field_bits, - "Failed check for DRAM Density Ratio") ); + // Find map value + constexpr size_t UNDEFINED = 3; // JEDEC map doesn't go beyond 3 + + FAPI_TRY( mss::check::spd:: fail_for_invalid_value(i_target, + l_field_bits < UNDEFINED, + BYTE_INDEX, + l_field_bits, + "Failed check for DRAM Density Ratio") ); FAPI_DBG("%s. DRAM Density Ratio: %d", mss::c_str(i_target), @@ -1657,24 +1607,19 @@ fapi_try_exit: /// /// @brief Decodes Secondary SDRAM die count /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value die count -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 10 (bits 6~4) /// @note Item JC-45-2220.01x /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::sec_sdram_die_count(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - - constexpr size_t BYTE_INDEX = 5; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - // Buffer used for bit manipulation + constexpr size_t BYTE_INDEX = 5; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; fapi2::buffer l_spd_buffer(l_raw_byte); // Trace in the front assists w/ debug @@ -1684,16 +1629,19 @@ fapi2::ReturnCode decoder::sec_sdram_die_count(const fapi2::Target(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(SEC_DIE_COUNT_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Secondary Die Count") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(SEC_DIE_COUNT_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Secondary Die Count") ); FAPI_DBG("%s. Secondary Die Count: %d", mss::c_str(i_target), @@ -1706,25 +1654,19 @@ fapi_try_exit: /// /// @brief Decodes Secondary SDRAM package type /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing package type -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 10 (bit 7) /// @note Item JC-45-2220.01x /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::sec_sdram_package_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - - constexpr size_t BYTE_INDEX = 5; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + constexpr size_t BYTE_INDEX = 5; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", @@ -1733,16 +1675,20 @@ fapi2::ReturnCode decoder::sec_sdram_package_type(const fapi2::Target l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(SEC_PACKAGE_TYPE_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Secondary Package Type") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(SEC_PACKAGE_TYPE_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Secondary Package Type") ); FAPI_DBG("%s. Secondary Package Type: %d", mss::c_str(i_target), @@ -1756,43 +1702,40 @@ fapi_try_exit: /// /// @brief Decode Module Nominal Voltage, VDD /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if 1.2V is operable -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 11 (bit 0) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::operable_nominal_voltage(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 11; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(OPERABLE_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Endur") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(OPERABLE_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Endur") ); FAPI_DBG("%s. Operable: %d", mss::c_str(i_target), @@ -1805,43 +1748,40 @@ fapi_try_exit: /// /// @brief Decode Module Nominal Voltage, VDD /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if 1.2V is endurant -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 11 (bit 1) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::endurant_nominal_voltage(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 11; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(ENDURANT_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Endurant") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(ENDURANT_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Endurant") ); FAPI_DBG("%s. Endurant: %d", mss::c_str(i_target), @@ -1854,43 +1794,40 @@ fapi_try_exit: /// /// @brief Decodes SDRAM device width /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value device width in bits -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 12 (bits 2~0) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::device_width(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 12; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); - - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_field_bits = 0; l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(DEVICE_WIDTH_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Device Width") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(DEVICE_WIDTH_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Device Width") ); FAPI_DBG("%s. Device Width: %d", mss::c_str(i_target), @@ -1904,43 +1841,39 @@ fapi_try_exit: /// /// @brief Decodes number of package ranks per DIMM /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value number of package ranks per DIMM -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 12 (bits 5~3) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::num_package_ranks_per_dimm(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 12; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); - - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits - l_spd_buffer.extractToRight(l_field_bits); + fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_field_bits = 0; FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(NUM_PACKAGE_RANKS_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Num Package Ranks Per DIMM") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(NUM_PACKAGE_RANKS_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Num Package Ranks Per DIMM") ); FAPI_DBG("%s. Num Package Ranks per DIMM: %d", mss::c_str(i_target), @@ -1953,45 +1886,42 @@ fapi_try_exit: /// /// @brief Decodes Rank Mix /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value rank mix value from SPD -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 12 (bit 6) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::rank_mix(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 12; - constexpr size_t INVALID_VALUE = 2; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); - - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - (l_field_bits < INVALID_VALUE), - BYTE_INDEX, - l_field_bits, - "Failed check for Rank Mix") ); + // Find map value + constexpr size_t INVALID_VALUE = 2; + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + (l_field_bits < INVALID_VALUE), + BYTE_INDEX, + l_field_bits, + "Failed check for Rank Mix") ); + + // Update output after check passes o_value = l_field_bits; FAPI_DBG("%s. Rank Mix: %d", @@ -2006,42 +1936,41 @@ fapi_try_exit: /// /// @brief Decodes primary bus width /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value primary bus width in bits -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 13 (bits 2~0) /// @note Item JC-45-2220.01x /// @note Page 27 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::prim_bus_width(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - constexpr size_t BYTE_INDEX = 13; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); // Trace in the front assists w/ debug + constexpr size_t BYTE_INDEX = 13; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; + FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_field_bits = 0; l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(BUS_WIDTH_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Primary Bus Width") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(BUS_WIDTH_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Primary Bus Width") ); FAPI_DBG("%s. Primary Bus Width: %d", mss::c_str(i_target), @@ -2054,42 +1983,40 @@ fapi_try_exit: /// /// @brief Decodes bus width extension /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value bus width extension in bits -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 13 (bits 2~0) /// @note Item JC-45-2220.01x /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::bus_width_extension(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 13; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(BUS_WIDTH_EXT_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Bus Width Extension") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(BUS_WIDTH_EXT_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Bus Width Extension") ); FAPI_DBG("%s. Bus Width Extension (bits): %d", mss::c_str(i_target), @@ -2103,44 +2030,41 @@ fapi_try_exit: /// /// @brief Decode Module Thermal Sensor /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value thermal sensor value from SPD -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 14 (bit 7) /// @note Item JC-45-2220.01x /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::thermal_sensor(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 14; - constexpr size_t INVALID_VALUE = 2; // single bit value 0 or 1 - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - l_field_bits < INVALID_VALUE, - BYTE_INDEX, - l_field_bits, - "Failed check for Thermal Sensor") ); + // Check for valid value + constexpr size_t INVALID_VALUE = 2; // single bit value 0 or 1 + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_field_bits < INVALID_VALUE, + BYTE_INDEX, + l_field_bits, + "Failed check for Thermal Sensor") ); + + // Update output after check passes o_value = l_field_bits; FAPI_DBG("%s. Thermal Sensor: %d", @@ -2154,45 +2078,43 @@ fapi_try_exit: /// /// @brief Decode Extended Base Module Type /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value raw data from SPD -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 15 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::extended_base_module_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint8_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 15; - constexpr size_t RESERVED = 0; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); - - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); + l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); + // Check for valid value // Currently reserved to 0b000 - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - l_field_bits == RESERVED, - BYTE_INDEX, - l_field_bits, - "Failed check for Extended Base Module Type") ); + constexpr size_t RESERVED = 0; + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_field_bits == RESERVED, + BYTE_INDEX, + l_field_bits, + "Failed check for Extended Base Module Type") ); + + // Update output for check passes o_value = l_field_bits; FAPI_DBG("%s. Extended Base Module Type: %d", @@ -2207,43 +2129,40 @@ fapi_try_exit: /// /// @brief Decode Fine Timebase /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value fine_timebase from SPD in picoseconds -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 17 (bits 1~0) /// @note Item JC-45-2220.01x /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_timebase(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 17; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); - - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(FINE_TIMEBASE_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Fine Timebase") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(FINE_TIMEBASE_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Fine Timebase") ); FAPI_DBG("%s. Fine Timebase: %d", mss::c_str(i_target), @@ -2256,43 +2175,40 @@ fapi_try_exit: /// /// @brief Decode Medium Timebase /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value medium timebase from SPD in picoseconds -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 17 (bits 3~2) /// @note Item JC-45-2220.01x /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::medium_timebase(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { - + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 17; - uint8_t l_raw_byte = i_spd_data[BYTE_INDEX]; - uint8_t l_field_bits = 0; - - // Buffer used for bit manipulation - fapi2::buffer l_spd_buffer(l_raw_byte); + uint8_t l_raw_byte = iv_spd_data[BYTE_INDEX]; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, l_raw_byte); // Extracting desired bits + uint8_t l_field_bits = 0; + fapi2::buffer l_spd_buffer(l_raw_byte); l_spd_buffer.extractToRight(l_field_bits); FAPI_DBG("Field Bits value: %d", l_field_bits); - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - mss::find_value_from_key(MEDIUM_TIMEBASE_MAP, l_field_bits, o_value), - BYTE_INDEX, - l_field_bits, - "Failed check for Medium Timebase") ); + // Find map value + bool l_is_val_found = mss::find_value_from_key(MEDIUM_TIMEBASE_MAP, l_field_bits, o_value); + + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + l_is_val_found, + BYTE_INDEX, + l_field_bits, + "Failed check for Medium Timebase") ); FAPI_DBG("%s. Medium Timebase: %d", mss::c_str(i_target), @@ -2306,9 +2222,8 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum Cycle Time in MTB /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 18 /// @note Item JC-45-2220.01x /// @note Page 31-32 @@ -2319,16 +2234,11 @@ fapi_try_exit: /// used for correction to get the actual value. /// fapi2::ReturnCode decoder::min_cycle_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { - constexpr size_t BYTE_INDEX = 18; - - constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC - // Explicit conversion - int64_t l_timing_val = int64_t(i_spd_data[BYTE_INDEX]); + constexpr size_t BYTE_INDEX = 18; + int64_t l_timing_val = int64_t(iv_spd_data[BYTE_INDEX]); // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: %d.", @@ -2336,13 +2246,16 @@ fapi2::ReturnCode decoder::min_cycle_time(const fapi2::Target= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the min cycle time (tckmin) in MTB") ); + // Check if value is valid + constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC + + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the min cycle time (tckmin) in MTB") ); // Update output after check passes o_value = l_timing_val; @@ -2358,9 +2271,8 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Maximum Cycle Time in MTB /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmax in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 19 /// @note Item JC-45-2220.01x /// @note Page 32 @@ -2371,16 +2283,11 @@ fapi_try_exit: /// used for correction to get the actual value. /// fapi2::ReturnCode decoder::max_cycle_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { - constexpr size_t BYTE_INDEX = 19; - - constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC - // Explicit conversion - int64_t l_timing_val = int64_t(i_spd_data[BYTE_INDEX]); + constexpr size_t BYTE_INDEX = 19; + int64_t l_timing_val = int64_t(iv_spd_data[BYTE_INDEX]); // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: %d.", @@ -2388,13 +2295,16 @@ fapi2::ReturnCode decoder::max_cycle_time(const fapi2::Target= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the max cycle time (tckmax) in MTB") ); + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC + + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the max cycle time (tckmax) in MTB") ); // Update output after check passes o_value = l_timing_val; @@ -2411,68 +2321,68 @@ fapi_try_exit: /// /// @brief Decode CAS Latencies Supported /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value bitmap of supported CAS latencies -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Bytes 20-23 /// @note Item JC-45-2220.01x /// @note Page 33-34 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::supported_cas_latencies(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint64_t& o_value) { - constexpr size_t FIRST_BYTE = 20; - constexpr size_t SEC_BYTE = 21; - constexpr size_t THIRD_BYTE = 22; - constexpr size_t FOURTH_BYTE = 23; - - constexpr size_t OUTPUT_START = 0; - constexpr size_t OUTPUT_LEN = 64; - - // Buffers used for bit manipulation - fapi2::buffer l_buffer; - // Trace print in the front assists w/ debug + constexpr size_t FIRST_BYTE = 20; + uint8_t first_raw_byte = iv_spd_data[FIRST_BYTE]; FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", c_str(i_target), FIRST_BYTE, - i_spd_data[FIRST_BYTE]); + first_raw_byte); + constexpr size_t SEC_BYTE = 21; + uint8_t sec_raw_byte = iv_spd_data[SEC_BYTE]; FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", c_str(i_target), SEC_BYTE, - i_spd_data[SEC_BYTE]); + sec_raw_byte); + constexpr size_t THIRD_BYTE = 22; + uint8_t third_raw_byte = iv_spd_data[THIRD_BYTE]; FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", c_str(i_target), THIRD_BYTE, - i_spd_data[THIRD_BYTE]) + third_raw_byte); + constexpr size_t FOURTH_BYTE = 23; + uint8_t fourth_raw_byte = iv_spd_data[FOURTH_BYTE]; FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", c_str(i_target), FOURTH_BYTE, - i_spd_data[FOURTH_BYTE]); + fourth_raw_byte); + // Buffers used for bit manipulation // Combine Bytes to create bitmap - right aligned - l_buffer.insertFromRight(i_spd_data[FIRST_BYTE]). - insertFromRight(i_spd_data[SEC_BYTE]). - insertFromRight(i_spd_data[THIRD_BYTE]). - insertFromRight(i_spd_data[FOURTH_BYTE]); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight(first_raw_byte) + .insertFromRight(sec_raw_byte) + .insertFromRight(third_raw_byte) + .insertFromRight(fourth_raw_byte); // According to the JEDEC spec: // Byte 23 bit 6 is reserved and must be coded as 0. - // Warn instead of fail because in last revision this was a reserved byte coded as 0x00 + // Should we warn instead of fail because in last revision this was a reserved byte coded as 0x00 constexpr size_t BIT_START = 33; // relative position of bit 6 in byte 23 relative to uint64_t constexpr size_t BIT_LEN = 1; + constexpr size_t OUTPUT_START = 0; + constexpr size_t OUTPUT_LEN = 64; - FAPI_TRY( mss::check::spd:: - fail_for_invalid_value(i_target, - !(l_buffer.getBit()), - FOURTH_BYTE, - i_spd_data[FOURTH_BYTE], - "Failed check on CAS latencies supported") ); + // Check for a valid value + FAPI_TRY( mss::check::spd::fail_for_invalid_value(i_target, + !(l_buffer.getBit()), + FOURTH_BYTE, + fourth_raw_byte, + "Failed check on CAS latencies supported") ); // Update output value only if range check passes l_buffer.extractToRight(o_value); @@ -2489,9 +2399,8 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum CAS Latency Time in MTB /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tAAmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 24 /// @note Item JC-45-2220.01x /// @note Page 34 @@ -2502,16 +2411,11 @@ fapi_try_exit: /// used for correction to get the actual value. /// fapi2::ReturnCode decoder::min_cas_latency_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { - constexpr size_t BYTE_INDEX = 24; - - constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC - // Explicit conversion - int64_t l_timing_val = int64_t(i_spd_data[BYTE_INDEX]); + constexpr size_t BYTE_INDEX = 24; + int64_t l_timing_val = int64_t(iv_spd_data[BYTE_INDEX]); // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", @@ -2519,13 +2423,16 @@ fapi2::ReturnCode decoder::min_cas_latency_time(const fapi2::Target= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum CAS Latency Time (tAAmin) in MTB") ); + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC + + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum CAS Latency Time (tAAmin) in MTB") ); // Only update output if it passes check o_value = l_timing_val; @@ -2541,9 +2448,8 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum RAS to CAS Delay Time in MTB /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCDmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 25 /// @note Item JC-45-2220.01x /// @note Page 35 @@ -2554,16 +2460,12 @@ fapi_try_exit: /// used for correction to get the actual value /// fapi2::ReturnCode decoder::min_ras_to_cas_delay_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + int64_t& o_value) { - constexpr size_t BYTE_INDEX = 25; - - constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC - // Explicit conversion - int64_t l_timing_val = int64_t(i_spd_data[BYTE_INDEX]); + constexpr size_t BYTE_INDEX = 25; + int64_t l_timing_val = int64_t(iv_spd_data[BYTE_INDEX]); // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", @@ -2571,13 +2473,16 @@ fapi2::ReturnCode decoder::min_ras_to_cas_delay_time(const fapi2::Target= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum RAS to CAS Delay Time (tRCDmin) in MTB") ); + // Find valid value + constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC + + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum RAS to CAS Delay Time (tRCDmin) in MTB") ); // Only update output if it passes check o_value = l_timing_val; @@ -2593,9 +2498,8 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum Row Precharge Delay Time in MTB /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRPmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 26 /// @note Item JC-45-2220.01x /// @note Page 36-37 @@ -2606,16 +2510,11 @@ fapi_try_exit: /// used for correction to get the actual value /// fapi2::ReturnCode decoder::min_row_precharge_delay_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { - constexpr size_t BYTE_INDEX = 26; - - constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC - // Explicit conversion - int64_t l_timing_val = int64_t(i_spd_data[BYTE_INDEX]); + constexpr size_t BYTE_INDEX = 26; + int64_t l_timing_val = int64_t(iv_spd_data[BYTE_INDEX]); // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", @@ -2623,13 +2522,16 @@ fapi2::ReturnCode decoder::min_row_precharge_delay_time(const fapi2::Target= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Row Precharge Delay Time (tRPmin) in MTB") ); + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC + + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Row Precharge Delay Time (tRPmin) in MTB") ); // Only update output if it passes check o_value = l_timing_val; @@ -2646,74 +2548,72 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum Active to Precharge Delay Time in MTB /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRASmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 27 (bits 3~0) & Byte 28 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 38 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::min_active_to_precharge_delay_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tRASmin's most significant nibble (MSN) - auto tRASmin_MSN = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRASmin_MSN = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 27; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); - fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits + uint8_t l_out = 0; + fapi2::buffer l_buffer(i_data[BYTE_INDEX]); l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tRASmin's least significant byte (LSB) - auto tRASmin_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRASmin_LSB = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 28; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); - fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits + uint8_t l_out = 0; + fapi2::buffer l_buffer(i_data[BYTE_INDEX]); l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSN_START = 52; constexpr size_t MSN_LEN = 4; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tRASmin_MSN(i_target, i_spd_data) ). - insertFromRight( tRASmin_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight( tRASmin_MSN(i_target, iv_spd_data) ). + insertFromRight( tRASmin_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -2726,13 +2626,12 @@ fapi2::ReturnCode decoder::min_active_to_precharge_delay_time(const fapi2::Targe // But byte 28 of the JEDEC spec explains how to piece this together - AAM constexpr size_t ERROR_BYTE_INDEX = 28; - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Active to Precharge Delay Time (tRASmin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Active to Precharge Delay Time (tRASmin) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -2749,9 +2648,8 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum Active to Active/Refresh Delay Time in MTB /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 27 (bits 7~4) & SPD Byte 29 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 38 @@ -2762,64 +2660,64 @@ fapi_try_exit: /// used for correction to get the actual value. /// fapi2::ReturnCode decoder::min_active_to_active_refresh_delay_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tRCmin's most significant nibble (MSN) - auto tRCmin_MSN = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRCmin_MSN = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 27; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tRCmin's least significant byte (LSB) - auto tRCmin_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRCmin_LSB = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 29; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); - fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits + uint8_t l_out = 0; + fapi2::buffer l_buffer(i_data[BYTE_INDEX]); l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSN_START = 52; constexpr size_t MSN_LEN = 4; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tRCmin_MSN(i_target, i_spd_data) ). - insertFromRight( tRCmin_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight( tRCmin_MSN(i_target, iv_spd_data) ). + insertFromRight( tRCmin_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -2832,13 +2730,12 @@ fapi2::ReturnCode decoder::min_active_to_active_refresh_delay_time(const fapi2:: // But byte 29 of the JEDEC spec explains how to piece this together - AAM constexpr size_t ERROR_BYTE_INDEX = 29; - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Active to Active/Refresh Delay Time (tRCmin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Active to Active/Refresh Delay Time (tRCmin) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -2855,73 +2752,72 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 1 /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC1min in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 30 & Byte 31 /// @note Item JC-45-2220.01x /// @note Page 39-40 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_1(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tRFC1min's most significant byte (MSB) - auto tRFC1min_MSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRFC1min_MSB = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 31; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tRFC1min's least significant byte (LSB) - auto tRFC1min_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRFC1min_LSB = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 30; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSB_START = 48; constexpr size_t MSB_LEN = 8; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tRFC1min_MSB(i_target, i_spd_data) ). - insertFromRight( tRFC1min_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight( tRFC1min_MSB(i_target, iv_spd_data) ). + insertFromRight( tRFC1min_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -2934,13 +2830,12 @@ fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_1(const fapi2::Target // Chose one of them (byte 30) to for error printout of this decode constexpr size_t ERROR_BYTE_INDEX = 30; - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Refresh Recovery Delay Time 1 (tRFC1min) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Refresh Recovery Delay Time 1 (tRFC1min) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -2956,73 +2851,70 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 2 /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC2min in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 32 & Byte 33 /// @note Item JC-45-2220.01x /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_2(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tRFC2min's most significant byte (MSB) - auto tRFC2min_MSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRFC2min_MSB = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 33; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); - fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits + uint8_t l_out = 0; + fapi2::buffer l_buffer(i_data[BYTE_INDEX]); l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tRFC2min's least significant byte (LSB) - auto tRFC2min_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRFC2min_LSB = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 32; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSB_START = 48; constexpr size_t MSB_LEN = 8; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tRFC2min_MSB(i_target, i_spd_data) ). - insertFromRight( tRFC2min_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight( tRFC2min_MSB(i_target, iv_spd_data) ). + insertFromRight( tRFC2min_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -3035,13 +2927,12 @@ fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_2(const fapi2::Target // Chose one of them (byte 33) to for error printout of this decode constexpr size_t ERROR_BYTE_INDEX = 33; - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Refresh Recovery Delay Time 2 (tRFC2min) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Refresh Recovery Delay Time 2 (tRFC2min) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -3057,73 +2948,71 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 4 /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC4min in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 34 & Byte 35 /// @note Item JC-45-2220.01x /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_4(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tRFC4min's most significant byte (MSB) - auto tRFC4min_MSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRFC4min_MSB = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 35; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tRFC4min's least significant byte (LSB) - auto tRFC4min_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tRFC4min_LSB = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 34; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSB_START = 48; constexpr size_t MSB_LEN = 8; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tRFC4min_MSB(i_target, i_spd_data) ). - insertFromRight( tRFC4min_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight( tRFC4min_MSB(i_target, iv_spd_data) ). + insertFromRight( tRFC4min_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -3136,13 +3025,12 @@ fapi2::ReturnCode decoder::min_refresh_recovery_delay_time_4(const fapi2::Target // Chose one of them (byte 34) for error printout of this decode constexpr size_t ERROR_BYTE_INDEX = 34; - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Refresh Recovery Delay Time 4 (tRFC4min) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Refresh Recovery Delay Time 4 (tRFC4min) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -3158,73 +3046,71 @@ fapi_try_exit: /// /// @brief Decodes SDRAM Minimum Four Activate Window Delay Time /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tFAWmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 36 (bits 3~0) & Byte 37 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 42 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::min_tfaw(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tFAWmin's most significant nibble (MSN) - auto tFAWmin_MSN = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tFAWmin_MSN = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 36; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tFAWmin's least significant byte (LSB) - auto tFAWmin_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tFAWmin_LSB = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 37; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSN_START = 52; constexpr size_t MSN_LEN = 4; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tFAWmin_MSN(i_target, i_spd_data) ). - insertFromRight( tFAWmin_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight( tFAWmin_MSN(i_target, iv_spd_data) ). + insertFromRight( tFAWmin_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -3237,13 +3123,12 @@ fapi2::ReturnCode decoder::min_tfaw(const fapi2::Target& i_tar // Chose one of them (byte 37) to for error printout of this decode constexpr size_t ERROR_BYTE_INDEX = 37; - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Four Activate Window Delay Time (tFAWmin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Four Activate Window Delay Time (tFAWmin) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -3259,9 +3144,8 @@ fapi_try_exit: /// /// @brief Decodes Minimum Activate to Activate Delay Time - Different Bank Group /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Smin MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 38 /// @note Item JC-45-2220.01x /// @note Page 43 @@ -3272,31 +3156,30 @@ fapi_try_exit: /// used for correction to get the actual value. /// fapi2::ReturnCode decoder::min_trrd_s(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 38; - constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC + FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", + mss::c_str(i_target), + BYTE_INDEX, + iv_spd_data[BYTE_INDEX]); // Retrieve Minimum Activate to Activate Delay Time - Different Bank Group // explicit conversion to int64_t - int64_t l_timing_val = int64_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int64_t(iv_spd_data[BYTE_INDEX]); - // Trace in the front assists w/ debug - FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", - mss::c_str(i_target), - BYTE_INDEX, - l_timing_val); + // Find valid value + constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on Minimum Activate to Activate Delay Time - Different Bank Group (tRRD_Smin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on Minimum Activate to Activate Delay Time - Different Bank Group (tRRD_Smin) in MTB") ); // Update output value only if range check passes o_value = l_timing_val; @@ -3312,9 +3195,8 @@ fapi_try_exit: /// /// @brief Decodes Minimum Activate to Activate Delay Time - Same Bank Group /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Lmin MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 39 /// @note Item JC-45-2220.01x /// @note Page 43-44 @@ -3325,31 +3207,30 @@ fapi_try_exit: /// used for correction to get the actual value. /// fapi2::ReturnCode decoder::min_trrd_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 39; - constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC + FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", + mss::c_str(i_target), + BYTE_INDEX, + iv_spd_data[BYTE_INDEX]); // Retrieve Minimum Activate to Activate Delay Time - Same Bank Group // explicit conversion to int64_t - int64_t l_timing_val = int64_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int64_t(iv_spd_data[BYTE_INDEX]); - // Trace in the front assists w/ debug - FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", - mss::c_str(i_target), - BYTE_INDEX, - l_timing_val); + // Find valid value + constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on Minimum Activate to Activate Delay Time - Same Bank Group (tRRD_Lmin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on Minimum Activate to Activate Delay Time - Same Bank Group (tRRD_Lmin) in MTB") ); // Update output value only if range check passes o_value = l_timing_val; @@ -3365,9 +3246,8 @@ fapi_try_exit: /// /// @brief Decodes Minimum CAS to CAS Delay Time - Same Bank Group /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tCCD_Lmin MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 40 /// @note Item JC-45-2220.01x /// @note Page 44-45 @@ -3378,31 +3258,30 @@ fapi_try_exit: /// used for correction to get the actual value. /// fapi2::ReturnCode decoder::min_tccd_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 40; - constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC + FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", + mss::c_str(i_target), + BYTE_INDEX, + iv_spd_data[BYTE_INDEX]); // Retrieve Minimum CAS to CAS Delay Time - Same Bank Group // explicit conversion to int64_t - int64_t l_timing_val = int64_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int64_t(iv_spd_data[BYTE_INDEX]); - // Trace in the front assists w/ debug - FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", - mss::c_str(i_target), - BYTE_INDEX, - l_timing_val); + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = 1; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 255; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on Minimum CAS to CAS Delay Time - Same Bank Group (tCCD_Lmin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on Minimum CAS to CAS Delay Time - Same Bank Group (tCCD_Lmin) in MTB") ); // Update output value only if range check passes o_value = l_timing_val; @@ -3418,73 +3297,72 @@ fapi_try_exit: /// /// @brief Decodes Minimum Write Recovery Time /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 41 (bits 3~0) & Byte 42 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::min_write_recovery_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tWRmin's most nibble byte (MSN) - auto tWRmin_MSN = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tWRmin_MSN = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 41; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tWRmin's least significant byte (LSB) - auto tWRmin_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tWRmin_LSB = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 42; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSN_START = 52; constexpr size_t MSN_LEN = 4; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tWRmin_MSN(i_target, i_spd_data) ). - insertFromRight( tWRmin_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + l_buffer.insertFromRight( tWRmin_MSN(i_target, iv_spd_data) ). + insertFromRight( tWRmin_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -3500,13 +3378,12 @@ fapi2::ReturnCode decoder::min_write_recovery_time(const fapi2::Target= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Write Recovery Time (tWRmin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Write Recovery Time (tWRmin) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -3523,73 +3400,71 @@ fapi_try_exit: /// /// @brief Decodes Minimum Write to Read Time - Different Bank Group /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRT_Smin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 43 (bits 3~0) & Byte 44 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::min_twtr_s(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tWRT_Smin's most nibble byte (MSN) - auto tWRT_Smin_MSN = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tWRT_Smin_MSN = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 43; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tWRT_Smin's least significant byte (LSB) - auto tWRT_Smin_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tWRT_Smin_LSB = [](const fapi2::Target& i_target, const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 44; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSN_START = 52; constexpr size_t MSN_LEN = 4; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tWRT_Smin_MSN(i_target, i_spd_data) ). - insertFromRight( tWRT_Smin_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight( tWRT_Smin_MSN(i_target, iv_spd_data) ). + insertFromRight( tWRT_Smin_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -3606,13 +3481,12 @@ fapi2::ReturnCode decoder::min_twtr_s(const fapi2::Target& i_t // Chose one of them (byte 44) to for error printout of this decode constexpr size_t ERROR_BYTE_INDEX = 44; - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Write to Read Time - Different Bank Group (tWRT_Smin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Write to Read Time - Different Bank Group (tWRT_Smin) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -3628,73 +3502,73 @@ fapi_try_exit: /// /// @brief Decodes Minimum Write to Read Time - Same Bank Group /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRT_Lmin in MTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 43 (bits 7~4) & Byte 45 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 46 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::min_twtr_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { // Lambda expression to retrieve tWRT_Lmin's most nibble byte (MSN) - auto tWRT_Lmin_MSN = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tWRT_Lmin_MSN = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 43; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; // Lambda expression to retrieve tWRT_Lmin's least significant byte (LSB) - auto tWRT_Lmin_LSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto tWRT_Lmin_LSB = [](const fapi2::Target& i_target, + const std::vector& i_data) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 45; - uint8_t l_out = 0; - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, i_data[BYTE_INDEX]); + // Extracting desired bits + uint8_t l_out = 0; fapi2::buffer l_buffer(i_data[BYTE_INDEX]); - // Extracting desired bits l_buffer.extractToRight(l_out); return l_out; }; - int64_t l_timing_val = 0; - fapi2::buffer l_buffer; - // Combining bits to create timing value (in a buffer) constexpr size_t MSN_START = 52; constexpr size_t MSN_LEN = 4; constexpr size_t LSB_START = 56; constexpr size_t LSB_LEN = 8; - l_buffer.insertFromRight( tWRT_Lmin_MSN(i_target, i_spd_data) ). - insertFromRight( tWRT_Lmin_LSB(i_target, i_spd_data) ); + fapi2::buffer l_buffer; + + l_buffer.insertFromRight( tWRT_Lmin_MSN(i_target, iv_spd_data) ). + insertFromRight( tWRT_Lmin_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; constexpr size_t OUTPUT_LEN = 64; + int64_t l_timing_val = 0; l_buffer.extractToRight(l_timing_val); @@ -3709,13 +3583,12 @@ fapi2::ReturnCode decoder::min_twtr_l(const fapi2::Target& i_t // Chose one of them (byte 45) to for error printout of this decode constexpr size_t ERROR_BYTE_INDEX = 45; - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - ERROR_BYTE_INDEX, - l_timing_val, - "Failed check on the Minimum Write to Read Time - Same Bank Group (tWRT_Lmin) in MTB") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + ERROR_BYTE_INDEX, + l_timing_val, + "Failed check on the Minimum Write to Read Time - Same Bank Group (tWRT_Lmin) in MTB") ); // Update output only after check passes o_value = l_timing_val; @@ -3731,40 +3604,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for Minimum CAS to CAS Delay Time - Same Bank Group /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tCCD_Lmin offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 117 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_min_tccd_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 117; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for Minimum CAS to CAS Delay Time // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); + + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the fine offset for min RAS to CAS Delay Time (tCCD_Lmin)") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the fine offset for min RAS to CAS Delay Time (tCCD_Lmin)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -3780,40 +3652,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Same Bank Group /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Lmin offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 118 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_min_trrd_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 118; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for Minimum Activate to Activate Delay Time // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the fine offset for Minimum Activate to Activate Delay Time (tRRD_Lmin)") ); + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC + + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the fine offset for Minimum Activate to Activate Delay Time (tRRD_Lmin)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -3829,40 +3700,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Different Bank Group /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Smin offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 119 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_min_trrd_s(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 119; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for Minimum Activate to Activate Delay Time - Different Bank Group // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); + + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the fine offset for Minimum Activate to Activate Delay Time - Different Bank Group (tRRD_Smin)") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the fine offset for Minimum Activate to Activate Delay Time - Different Bank Group (tRRD_Smin)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -3878,40 +3748,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for Minimum Active to Active/Refresh Delay Time /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCmin offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 120 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_min_trc(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 120; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for Minimum Active to Active/Refresh Delay Time // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); + + // Check for vali value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the fine offset for Minimum Active to Active/Refresh Delay Time (tRCmin)") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the fine offset for Minimum Active to Active/Refresh Delay Time (tRCmin)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -3927,40 +3796,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for Minimum Row Precharge Delay Time /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRPmin offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 121 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_min_trp(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 121; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for Minimum Row Precharge Delay Time // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); + + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the fine offset for Minimum Row Precharge Delay Time (tRPmin)") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the fine offset for Minimum Row Precharge Delay Time (tRPmin)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -3975,40 +3843,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for SDRAM Minimum RAS to CAS Delay Time /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCDmin offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 122 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_min_trcd(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 122; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for SDRAM Minimum RAS to CAS Delay Time // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the fine offset for min RAS to CAS Delay Time (tRCDmin)") ); + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC + + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the fine offset for min RAS to CAS Delay Time (tRCDmin)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -4024,40 +3891,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for SDRAM Minimum CAS Latency Time /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tAAmin offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 123 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_min_taa(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 125; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for SDRAM Minimum CAS Latency Time // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); + + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the Fine offset for Minimum CAS Latency Time (tAAmin)") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the Fine offset for Minimum CAS Latency Time (tAAmin)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -4073,40 +3939,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for SDRAM Maximum Cycle Time /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmax offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 124 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_max_tck(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 124; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for SDRAM Maximum Cycle Time // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); + + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the fine offset for max cycle time (tckmax)") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the fine offset for max cycle time (tckmax)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -4123,40 +3988,39 @@ fapi_try_exit: /// /// @brief Decodes Fine Offset for SDRAM Minimum Cycle Time /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmin offset in FTB units -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 125 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::fine_offset_min_tck(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value) { + // Trace in the front assists w/ debug constexpr size_t BYTE_INDEX = 125; - constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC - constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - // Trace in the front assists w/ debug FAPI_DBG("%s SPD data at Byte %d: 0x%llX.", mss::c_str(i_target), BYTE_INDEX, - i_spd_data[BYTE_INDEX]); + iv_spd_data[BYTE_INDEX]); // Retrieve Fine Offset for SDRAM Minimum Cycle Time // int8_t conversion - allows me to get a negative offset // then implicit conversion to int64_t - int64_t l_timing_val = int8_t(i_spd_data[BYTE_INDEX]); + int64_t l_timing_val = int8_t(iv_spd_data[BYTE_INDEX]); + + // Check for valid value + constexpr int64_t TIMING_LOWER_BOUND = -128; // from JEDEC + constexpr int64_t TIMING_UPPER_BOUND = 127; // from JEDEC - FAPI_TRY(mss::check::spd:: - fail_for_invalid_value(i_target, - (l_timing_val <= TIMING_UPPER_BOUND) && - (l_timing_val >= TIMING_LOWER_BOUND), - BYTE_INDEX, - l_timing_val, - "Failed check on the Fine offset for Minimum Cycle Time (tCKmin)") ); + FAPI_TRY(mss::check::spd::fail_for_invalid_value(i_target, + (l_timing_val <= TIMING_UPPER_BOUND) && + (l_timing_val >= TIMING_LOWER_BOUND), + BYTE_INDEX, + l_timing_val, + "Failed check on the Fine offset for Minimum Cycle Time (tCKmin)") ); // Update output value only if range check passes o_value = l_timing_val; @@ -4173,20 +4037,19 @@ fapi_try_exit: /// /// @brief Decodes Cyclical Redundancy Code (CRC) for Base Configuration Section /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob /// @param[out] o_value crc value from SPD -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 127 & Byte 126 /// @note Item JC-45-2220.01x /// @note Page 53 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode decoder::cyclical_redundancy_code(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint16_t& o_value) { // Lambda expression to retrieve crc's most significant byte (MSB) - auto crc_MSB = [](const fapi2::Target& i_target, const uint8_t* i_data) + auto crc_MSB = [](const fapi2::Target& i_target, + const std::vector& i_data) { constexpr size_t BYTE_INDEX = 127; uint8_t l_out = 0; @@ -4206,7 +4069,8 @@ fapi2::ReturnCode decoder::cyclical_redundancy_code(const fapi2::Target& i_target, const uint8_t* i_data) + auto crc_LSB = [](const fapi2::Target& i_target, + const std::vector& i_data) { constexpr size_t BYTE_INDEX = 126; uint8_t l_out = 0; @@ -4232,8 +4096,8 @@ fapi2::ReturnCode decoder::cyclical_redundancy_code(const fapi2::Target( crc_MSB(i_target, i_spd_data) ). - insertFromRight( crc_LSB(i_target, i_spd_data) ); + l_buffer.insertFromRight( crc_MSB(i_target, iv_spd_data) ). + insertFromRight( crc_LSB(i_target, iv_spd_data) ); // Extract timing value from the buffer into an integral type constexpr size_t OUTPUT_START = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H index bbc47c784..6f983686b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_decoder.H @@ -40,7 +40,6 @@ namespace mss namespace spd { -using fapi2::TARGET_TYPE_DIMM; enum BYTE_EXTRACT : uint64_t { @@ -345,7 +344,7 @@ class decoder { public: - std::shared_ptr iv_spd_data; + std::vector iv_spd_data; // Constructor decoder() = default; @@ -360,449 +359,384 @@ class decoder /// /// @brief Decodes number of used SPD bytes /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value number of SPD bytes used - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 0 (3~0) /// @note Item JC-45-2220.01x /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode number_of_used_bytes(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode number_of_used_bytes(const fapi2::Target& i_target, uint16_t& o_value); /// /// @brief Decodes total number of SPD bytes /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value number of total SPD bytes - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 0 (bits 6~4) /// @note Item JC-45-2220.01x /// @note Page 14 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode number_of_total_bytes(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode number_of_total_bytes(const fapi2::Target& i_target, uint16_t& o_value); /// /// @brief Decodes DRAM Device Type /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value dram device type enumeration - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 2 /// @note Item JC-45-2220.01x /// @note Page 16 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode dram_device_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode dram_device_type(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes hybrid media field from SPD /// @param[in] i_target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 3 (bits 6~4) /// @note Item JC-45-2220.01x /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode hybrid_media(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode hybrid_media(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes hybrid field from SPD /// @param[in] i_target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 3 (bit 7) /// @note Item JC-45-2220.01x /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode hybrid(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode hybrid(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes SDRAM density from SPD /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value SDRAM density in GBs - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 4 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sdram_density(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode sdram_density(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes number of SDRAM banks from SPD /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value Number of SDRAM banks - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 4 (bits 5~4) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode banks(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode banks(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes number of SDRAM bank groups from SPD /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value Number of SDRAM bank groups - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 4 (bits 7~6) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode bank_groups(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode bank_groups(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes number of SDRAM column address bits /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 5 (bits 2~0) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode column_address_bits(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode column_address_bits(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes number of SDRAM row address bits /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 5 (bits 5~3) /// @note Item JC-45-2220.01x /// @note Page 18 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode row_address_bits(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode row_address_bits(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes Primary SDRAM signal loading /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 6 (bits 1~0) /// @note Item JC-45-2220.01x /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_signal_loading(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode prim_sdram_signal_loading(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes Primary SDRAM die count /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 6 (bits 6~4) /// @note Item JC-45-2220.01x /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_die_count(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode prim_sdram_die_count(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes Primary SDRAM package type /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 6 (bit 7) /// @note Item JC-45-2220.01x /// @note Page 19 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_sdram_package_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode prim_sdram_package_type(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decode SDRAM Maximum activate count /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 7 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode maximum_activate_count(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode maximum_activate_count(const fapi2::Target& i_target, uint32_t& o_value); /// /// @brief Decode SDRAM Maximum activate window (multiplier), tREFI uknown at this point /// @param[in] i_target - /// @param[in] i_spd_data - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 7 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 20 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode maximum_activate_window_multiplier(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode maximum_activate_window_multiplier(const fapi2::Target& i_target, uint32_t& o_value); /// /// @brief Decode Soft post package repair (soft PPR) /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 9 (bit 5) /// @note Item JC-45-2220.01x /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode soft_post_package_repair(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode soft_post_package_repair(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decode Post package repair (PPR) /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 9 (bits 7~6) /// @note Item JC-45-2220.01x /// @note Page 21 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode post_package_repair(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode post_package_repair(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes Secondary SDRAM signal loading /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 10 (bits 1~0) /// @note Item JC-45-2220.01x /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_signal_loading(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode sec_sdram_signal_loading(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes Secondary DRAM Density Ratio /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 10 (bits 3~2) /// @note Item JC-45-2220.01x /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_dram_density_ratio(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode sec_dram_density_ratio(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes Secondary SDRAM die count /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 10 (bits 6~4) /// @note Item JC-45-2220.01x /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_die_count(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode sec_sdram_die_count(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes Secondary SDRAM package type /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 10 (bit 7) /// @note Item JC-45-2220.01x /// @note Page 22 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode sec_sdram_package_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode sec_sdram_package_type(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decode Module Nominal Voltage, VDD /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if 1.2V is operable - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 11 (bit 0) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode operable_nominal_voltage(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode operable_nominal_voltage(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decode Module Nominal Voltage, VDD /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value enum representing if 1.2V is endurant - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 11 (bit 1) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode endurant_nominal_voltage(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode endurant_nominal_voltage(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes SDRAM device width /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value device width in bits - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 12 (bits 2~0) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode device_width(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode device_width(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes number of package ranks per DIMM /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value number of package ranks per DIMM - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 12 (bits 5~3) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode num_package_ranks_per_dimm(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode num_package_ranks_per_dimm(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes Rank Mix /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value rank mix value from SPD - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 12 (bit 6) /// @note Item JC-45-2220.01x /// @note Page 23 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode rank_mix(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode rank_mix(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes primary bus width /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value primary bus width in bits - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 13 (bits 2~0) /// @note Item JC-45-2220.01x /// @note Page 27 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode prim_bus_width(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode prim_bus_width(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decodes bus width extension - /// @param[in] i_target dimm targetn - /// @param[in] i_spd_data SPD blob + /// @param[in] i_target dimm target /// @param[out] o_value bus width extension in bits - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 13 (bits 4~3) /// @note Item JC-45-2220.01x /// @note Page 27 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode bus_width_extension(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode bus_width_extension(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decode Module Thermal Sensor /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value thermal sensor value from SPD - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 14 (bit 7) /// @note Item JC-45-2220.01x /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode thermal_sensor(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode thermal_sensor(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decode Extended Base Module Type /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value extended base module type value from SPD - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 15 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 28 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode extended_base_module_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode extended_base_module_type(const fapi2::Target& i_target, uint8_t& o_value); /// /// @brief Decode Fine Timebase /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value fine_timebase from SPD in picoseconds - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 17 (bits 1~0) /// @note Item JC-45-2220.01x /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_timebase(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode fine_timebase(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decode Medium Timebase /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value fine_timebase from SPD in picoseconds - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 17 (bits 3~2) /// @note Item JC-45-2220.01x /// @note Page 29 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode medium_timebase(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode medium_timebase(const fapi2::Target& i_target, int64_t& o_value); /// /// /// @brief Decodes SDRAM Minimum Cycle Time in MTB /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 18 /// @note Item JC-45-2220.01x /// @note Page 31-32 @@ -813,15 +747,13 @@ class decoder /// used for correction to get the actual value. /// virtual fapi2::ReturnCode min_cycle_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decodes SDRAM Maximum Cycle Time in MTB /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmax in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 19 /// @note Item JC-45-2220.01x /// @note Page 32 @@ -832,28 +764,24 @@ class decoder /// used for correction to get the actual value. /// virtual fapi2::ReturnCode max_cycle_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decode CAS Latencies Supported /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value bitmap of supported CAS latencies - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Bytes 20-23 /// @note Item JC-45-2220.01x /// @note Page 33-34 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode supported_cas_latencies(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode supported_cas_latencies(const fapi2::Target& i_target, uint64_t& o_value); /// /// @brief Decodes SDRAM Minimum CAS Latency Time in MTB /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tAAmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 24 /// @note Item JC-45-2220.01x /// @note Page 34 @@ -864,14 +792,12 @@ class decoder /// used for correction to get the actual value. /// virtual fapi2::ReturnCode min_cas_latency_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum RAS to CAS Delay Time in MTB /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCDmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 25 /// @note Item JC-45-2220.01x /// @note Page 35 @@ -882,14 +808,12 @@ class decoder /// used for correction to get the actual value /// virtual fapi2::ReturnCode min_ras_to_cas_delay_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Row Precharge Delay Time in MTB /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRPmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 26 /// @note Item JC-45-2220.01x /// @note Page 36-37 @@ -900,28 +824,24 @@ class decoder /// used for correction to get the actual value /// virtual fapi2::ReturnCode min_row_precharge_delay_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Active to Precharge Delay Time in MTB /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRASmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 28 (bits 7~4) & SPD Byte 27 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 38 /// @note DDR4 SPD Document Release 3 /// virtual fapi2::ReturnCode min_active_to_precharge_delay_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Active to Active/Refresh Delay Time in MTB /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 27 (bits 7~4) & SPD Byte 29 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 38 @@ -931,71 +851,62 @@ class decoder /// integer and the Fine Offset for tRCmin (SPD byte 120) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_active_to_active_refresh_delay_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_active_to_active_refresh_delay_time(const fapi2::Target& + i_target, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 1 /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC1min in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 30 & Byte 31 /// @note Item JC-45-2220.01x /// @note Page 39-40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_refresh_recovery_delay_time_1(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_refresh_recovery_delay_time_1(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 2 /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC2min in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 32 & Byte 33 /// @note Item JC-45-2220.01x /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_refresh_recovery_delay_time_2(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_refresh_recovery_delay_time_2(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Refresh Recovery Delay Time 4 /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRFC4min in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 34 & Byte 35 /// @note Item JC-45-2220.01x /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_refresh_recovery_delay_time_4(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_refresh_recovery_delay_time_4(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes SDRAM Minimum Four Activate Window Delay Time /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tFAWmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 36 (bits 3~0) & Byte 37 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 42 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_tfaw(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_tfaw(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Minimum Activate to Activate Delay Time - Different Bank Group /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Smin MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 38 /// @note Item JC-45-2220.01x /// @note Page 43 @@ -1005,15 +916,13 @@ class decoder /// integer and the Fine Offset for tRRD_Smin (SPD byte 119) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_trrd_s(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_trrd_s(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Minimum Activate to Activate Delay Time - Same Bank Group /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Lmin MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 39 /// @note Item JC-45-2220.01x /// @note Page 43-44 @@ -1023,15 +932,13 @@ class decoder /// integer and the Fine Offset for tRRD_Lmin (SPD byte 118) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_trrd_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_trrd_l(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Minimum CAS to CAS Delay Time - Same Bank Group /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCCD_Lmin MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 40 /// @note Item JC-45-2220.01x /// @note Page 44-45 @@ -1041,192 +948,165 @@ class decoder /// integer and the Fine Offset for tCCD_Lmin (SPD byte 117) /// used for correction to get the actual value. /// - virtual fapi2::ReturnCode min_tccd_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_tccd_l(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Minimum Write Recovery Time /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 41 (bits 3~0) & Byte 42 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_write_recovery_time(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_write_recovery_time(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Minimum Write to Read Time - Different Bank Group /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRT_Smin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 43 (bits 3~0) & Byte 44 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 40 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twtr_s(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_twtr_s(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Minimum Write to Read Time - Same Bank Group /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tWRT_Lmin in MTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 43 (bits 7~4) & Byte 45 (bits 7~0) /// @note Item JC-45-2220.01x /// @note Page 46 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode min_twtr_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode min_twtr_l(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum CAS to CAS Delay Time - Same Bank Group /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCCD_Lmin offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 117 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_tccd_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode fine_offset_min_tccd_l(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Same Bank Group /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Lmin offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 118 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trrd_l(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode fine_offset_min_trrd_l(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum Activate to Activate Delay Time - Different Bank Group /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRRD_Smin offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 119 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trrd_s(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode fine_offset_min_trrd_s(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum Active to Active/Refresh Delay Time /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCmin offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 120 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trc(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode fine_offset_min_trc(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Fine Offset for Minimum Row Precharge Delay Time /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRPmin offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 121 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trp(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode fine_offset_min_trp(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Fine Offset for SDRAM Minimum RAS to CAS Delay Time /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tRCDmin offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 122 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// - virtual fapi2::ReturnCode fine_offset_min_trcd(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + virtual fapi2::ReturnCode fine_offset_min_trcd(const fapi2::Target& i_target, int64_t& o_value); /// /// @brief Decodes Fine Offset for SDRAM Minimum CAS Latency Time /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tAAmin offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 123 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// virtual fapi2::ReturnCode fine_offset_min_taa(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decodes Fine Offset for SDRAM Maximum Cycle Time /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmax offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 124 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// virtual fapi2::ReturnCode fine_offset_max_tck(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decodes Fine Offset for SDRAM Minimum Cycle Time /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value tCKmin offset in FTB units - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 125 /// @note Item JC-45-2220.01x /// @note Page 52 /// @note DDR4 SPD Document Release 3 /// virtual fapi2::ReturnCode fine_offset_min_tck(const fapi2::Target& i_target, - const uint8_t* i_spd_data, int64_t& o_value); /// /// @brief Decodes Cyclical Redundancy Code (CRC) for Base Configuration Section /// @param[in] i_target dimm target - /// @param[in] i_spd_data SPD blob /// @param[out] o_value crc value from SPD - /// @return fapi2::ReturnCode + /// @return FAPI2_RC_SUCCESS if okay /// @note SPD Byte 127 & Byte 126 /// @note Item JC-45-2220.01x /// @note Page 53 /// @note DDR4 SPD Document Release 3 /// virtual fapi2::ReturnCode cyclical_redundancy_code(const fapi2::Target& i_target, - const uint8_t* i_spd_data, uint16_t& o_value); };// decoder @@ -1238,62 +1118,63 @@ class decoder /// /// @brief Decodes SPD Revision encoding level /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob -/// @param[out] o_value revision number -/// @return fapi2::ReturnCode +/// @param[in] i_spd_data SPD data +/// @param[out] o_value encoding revision num +/// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 1 (3~0). /// @note Item JC-45-2220.01x /// @note Page 14-15 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode rev_encoding_level(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + const std::vector& i_spd_data, uint8_t& o_value); /// /// @brief Decodes SPD Revision additions level /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD blob -/// @param[out] o_value revision number -/// @return fapi2::ReturnCode +/// @param[out] o_value additions revision num +/// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 1 (bits 7~4). /// @note Item JC-45-2220.01x /// @note Page 14-15 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode rev_additions_level(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + const std::vector& i_spd_data, uint8_t& o_value); /// /// @brief Decodes base module type (DIMM type) from SPD /// @param[in] i_target dimm target -/// @param[in] i_spd_data SPD blob -/// @param[out] o_value -/// @return fapi2::ReturnCode +/// @param[in] i_spd_data SPD data +/// @param[out] o_value base module type +/// @return FAPI2_RC_SUCCESS if okay /// @note Decodes SPD Byte 3 (bits 3~0) /// @note Item JC-45-2220.01x /// @note Page 17 /// @note DDR4 SPD Document Release 3 /// fapi2::ReturnCode base_module_type(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + const std::vector& i_spd_data, uint8_t& o_value); /// -/// @brief Object factory to select correct decoder based on SPD revision & dimm type +/// @brief Object factory to select correct decoder /// @param[in] i_target dimm target /// @param[in] i_spd_data SPD data /// @param[out] o_fact_obj shared pointer to the factory object -/// @return fapi2::ReturnCode +/// @return FAPI2_RC_SUCCESS if okay +/// @note Factory dependent on SPD revision & dimm type /// fapi2::ReturnCode factory(const fapi2::Target& i_target, - const uint8_t* i_spd_data, + const std::vector& i_spd_data, std::shared_ptr& o_fact_obj); /// /// @brief Creates factory object & SPD data caches /// @param[in] i_target the fapi2 target -/// @param[out] o_factory_caches map of factory objects with a dimm pos key +/// @param[out] o_factory_caches map of factory objects with a dimm position key /// @return FAPI2_RC_SUCCESS if okay /// template -- cgit v1.2.1