From d27962f1bfbd74cde2eb3e643579e11db7ea77b5 Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Fri, 1 Mar 2019 14:27:34 -0500 Subject: Updates CCS to run with quad encoded chip select Change-Id: I29566f1a77d244fa7cbd600e7a83da9784a66f51 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72720 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: Louis Stermole Dev-Ready: STEPHEN GLANCY Reviewed-by: ANDRE A. MARIN Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72928 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell --- src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/shared') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index e61edfc78..db61b8afb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -211,6 +211,9 @@ enum ffdc_function_codes // LR training function DWL_CALL_OUT = 130, MREP_CALL_OUT = 131, + + + CCS_INST_CONFIGURE_RANK = 132, }; // Static consts describing the bits used in the cal_step_enable attribute -- cgit v1.2.1