From 62321660514419ab1413a7bbe61ce19bae442875 Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Fri, 17 Nov 2017 16:11:51 -0600 Subject: Worksaround AWAN simulation failure The DIMM behavioral model does not properly invert b-side inputs in the AWAN simulations. This patch sets removes initial pattern if simulation is enabled. Change-Id: Ie00f3fc91ae5a6e17514d378e1d4494ad5c1714b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49879 Tested-by: FSP CI Jenkins Dev-Ready: STEPHEN GLANCY Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej Reviewed-by: Louis Stermole Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49908 Reviewed-by: Hostboot Team Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../chips/p9/procedures/hwp/memory/lib/phy/mss_training.C | 11 +++++++++-- .../chips/p9/procedures/hwp/memory/lib/phy/mss_training.H | 3 ++- 2 files changed, 11 insertions(+), 3 deletions(-) (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/phy') diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index 9c7060c26..c7438b096 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -655,9 +655,10 @@ uint64_t custom_read_ctr::calculate_cycles( const fapi2::Target> steps_factory(const fapi2::buffer& i_cal_steps) +std::vector> steps_factory(const fapi2::buffer& i_cal_steps, const bool i_sim) { std::vector> l_steps; @@ -669,11 +670,17 @@ std::vector> steps_factory(const fapi2::buffer& } // INITIAL_PAT_WR - if(i_cal_steps.getBit()) + // Note: simulation contains a bug where the DDR4 model does not match the DDR4 hardware + // As such, if the simulation IPW bug is set, do not create a step for initial pattern write + if(!i_sim && i_cal_steps.getBit()) { FAPI_INF("Initial pattern write is enabled"); l_steps.push_back(std::make_shared()); } + else if(i_sim) + { + FAPI_INF("Initial pattern write was requested, but the simulation for it is bugged! Skipping IPW"); + } // DQS_ALIGN if(i_cal_steps.getBit()) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H index 24ebc0e71..37f756098 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.H @@ -690,9 +690,10 @@ class custom_read_ctr : public phy_step /// /// @brief Creates the vector of training steps to loop over /// @param[in] i_cal_steps - the bit mask of calibration steps +/// @param[in] i_sim - simulation mode or not /// @return a vector of the calibration steps to run /// -std::vector> steps_factory(const fapi2::buffer& i_cal_steps); +std::vector> steps_factory(const fapi2::buffer& i_cal_steps, const bool i_sim); } // ns training -- cgit v1.2.1